Structures involving a field-effect transistor and methods for forming a structure that involves a field-effect transistor. A substrate is provided that has a first conductivity type. A first semiconductor layer having a second conductivity type is formed on the substrate. A second semiconductor layer having the first conductivity type is formed on the first semiconductor layer. A field-effect transistor is formed that includes a fin having a plurality of nanosheet channel layers arranged in a vertical stack on the second semiconductor layer, and a gate structure wrapped about the nanosheet channel layers. The first semiconductor layer defines a first p-n junction with a portion of the substrate, and the second semiconductor layer defines a second p-n junction with the first semiconductor layer. The first p-n junction and the second p-n junction are arranged in vertical alignment with the gate structure and the nanosheet channel layers.

A bulk finFET with partial dielectric isolation is disclosed. The dielectric isolation is disposed underneath the channel, and essentially bounded by the channel, such that it does not extend laterally beyond the channel under the source and drain regions. This allows increased volume of SiGe source and drain stressor regions placed adjacent to the channel, allowing for a more strained channel, which improves carrier mobility. An N+ doped silicon region is disposed below the dielectric isolation and extends laterally beyond the channel and underneath the stressor source and drain regions, forming a reverse-biased p/n junction with the P+ doped source and drain SiGe stressor to minimize leakage currents from under the insulator.

The present application discloses a semiconductor device with a P-N junction isolation structure and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a first well layer positioned in the substrate and having a first electrical type, a bottom conductive layer positioned in the first well layer and having a second electrical type opposite to the first electrical type, a first insulating layer positioned on the bottom conductive layer, an isolation-mask layer positioned on the substrate and enclosing the first insulating layer, a first conductive line positioned on the first insulating layer, and a bias layer positioned in the first well layer and spaced apart from the bottom conductive layer. The bottom conductive layer, the first insulating layer, and the first conductive line together configure a programmable unit.

A Group III-nitride-based enhancement mode transistor includes a multi-heterojunction fin structure. A first side face of the multi-heterojunction fin structure is covered by a first p-type Group III-nitride layer, and a second side face of the multi-heterojunction fin structure is covered by a second p-type Group III-nitride layer.

High voltage semiconductor devices are described herein. An exemplary semiconductor device includes a first doped region and a second doped region disposed in a substrate. The first doped region and the second doped region are oppositely doped and adjacently disposed in the substrate. A first isolation structure and a second isolation structure are disposed over the substrate, such that each are disposed at least partially over the first doped region. The first isolation structure is spaced apart from the second isolation structure. A resistor is disposed over a portion of the first isolation structure and electrically coupled to the first doped region. A field plate disposed over a portion of the second doped region and electrically coupled to the second doped region.

A semiconductor device of the present invention achieves improved avoidance of a parasitic operation in a circuit region while achieving miniaturization of the semiconductor device and a reduction in the amount of time for manufacturing the semiconductor device. The semiconductor device according to the present invention includes an IGBT disposed on a first main surface of a semiconductor substrate provided with a drift layer of a first conductivity type; a thyristor disposed on the first main surface of the semiconductor substrate; a circuit region; a hole-current retrieval region separating the IGBT and the circuit region in a plan view; and a diffusion layer of a second conductivity type, the diffusion layer being disposed on a second main surface of the semiconductor substrate. The IGBT has an effective area equal to or less than an effective area of the thyristor in a plan view.

The present disclosure provides a method for fabricating a semiconductor device. The method includes providing a substrate, forming a first well layer in the substrate and having a first electrical type, forming an isolation-mask layer on the first well layer, forming mask openings along the isolation-mask layer to expose portions of the first well layer, forming bottom conductive layers in the portions of the first well layer, forming a bias layer in the first well layer and spaced apart from the bottom conductive layers, forming first insulating layers on the bottom conductive layers, forming first conductive lines on the first insulating layers and parallel to each other. The bottom conductive layers have a second electrical type opposite to the first electrical type. The bottom conductive layers, the first insulating layers, the first conductive lines together configure programmable units.

A semiconductor device and a method of manufacturing a semiconductor are provided. In an embodiment, a first trench is formed in a silicon carbide layer. A second trench is formed in the silicon carbide layer to define a mesa in the silicon carbide layer between the first trench and the second trench. A first doped semiconductor material is formed in the first trench and a second doped semiconductor material is formed in the second trench. A third doped semiconductor material is formed over the mesa to define a heterojunction at an interface between the third doped semiconductor material and the mesa.

A semiconductor device is provided that includes at least three regions. Each region includes a first-type layer doped with a first type of charge carriers and a second-type layer doped with a second type of charge carriers, and the first-type layer and the second-type layer are positioned laterally along each region. The first-type layer and the second-type layer have opposite polarity, and the first-type layer of a region is positioned substantially across the second-type layer of a neighboring region, and the second-type layer of a region is positioned substantially across the first-type layer of a neighboring region and each region includes a second-type well doped with the second type of charge carriers, and the second-type well is positioned around at least the first-type layer.

A circuit device includes core circuitry. The circuit device further includes a first plurality of guard rings having a first dopant type, wherein the first plurality of guard rings is around a periphery of the core circuitry. The circuit device further includes a second plurality of guard rings having a second dopant type, wherein the second dopant type is opposite to the first dopant type, and at least one guard ring of the second plurality of guard rings is around a periphery of at least one guard ring of the first plurality of guard rings.