A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a base and a fin structure over the base. The semiconductor device structure includes an isolation structure over the base and surrounding a lower portion of the fin structure. The semiconductor device structure includes a gate stack wrapped around an upper portion of the fin structure. The semiconductor device structure includes a source/drain structure partially embedded in the isolation structure and the lower portion of the fin structure. The source/drain structure has an undoped semiconductor layer and a first doped layer over the undoped semiconductor layer, and the undoped semiconductor layer separates the first doped layer from the isolation structure.

The present disclosure introduces a microelectronic device including a source side field plate in a microelectronic device. The microelectronic device may be configured as a metal oxide semiconductor (MOS) transistor, a laterally diffused metal oxide semiconductor (LDMOS) transistor, a drain extended metal oxide semiconductor (DEMOS) transistor, a bipolar junction transistor, a junction field effect transistor, a CMOS transistor, or a gated bipolar device. The source side field plate extends over the source region by a distance which is more than a quarter of the width of the source region. Transistors may suffer from Vt shifts during gate and drain stress over time. The source side field plate reduces the electric field of the transistor near the gate electrode corner on the source side of the transistor. The gate injection current on the source side and electron trapping in the gate oxide thereby reduced which reduces Vt shifts over time.

An integrated circuit device includes a semiconductor structure, a tunneling layer, a top electrode, a passivation layer, and a conductive feature. The semiconductor structure has a base portion and a protruding portion over a top surface of the base portion. The tunneling layer is over a top surface of the protruding portion of the semiconductor structure. The top electrode is over the tunneling layer. The passivation layer is over a sidewall of the protruding portion of the semiconductor structure. The conductive feature is directly below the protruding portion of the semiconductor structure.

A semiconductor device includes a substrate including an active pattern, a channel pattern on the active pattern and including semiconductor patterns, a source/drain pattern connected to the semiconductor patterns, a gate electrode on the semiconductor patterns, and a gate dielectric layer between the gate electrode and the semiconductor patterns. An inner spacer of the gate dielectric layer includes a horizontal portion between the high-k dielectric layer and the second semiconductor pattern, a vertical portion between the high-k dielectric layer and the source/drain pattern, and a corner portion between the horizontal portion and the vertical portion. A first thickness of the horizontal portion is less than a second thickness of the vertical portion. The second thickness of the vertical portion is less than a third thickness of the corner portion.

A semiconductor structure is provided. The semiconductor structure includes a gate structure over a substrate. The semiconductor structure also includes a gate spacer on a sidewall of the gate structure. The semiconductor structure also includes a source/drain feature adjacent to the gate structure. The semiconductor structure also includes a doped region extending along a bottom surface of the gate spacer. The source/drain feature has a curved sidewall connecting a top surface of the doped region and a bottom surface of the doped region.

A semiconductor device structure is provided. The semiconductor device structure includes a first stacked nanostructure and a second stacked nanostructure formed over a substrate. The semiconductor device structure includes a first gate structure formed over the first stacked nanostructure, and the first gate structure includes a first portion of a gate dielectric layer and a first portion of a filling layer. The semiconductor device structure includes a second gate structure formed over the second stacked nanostructure, and the second gate structure includes a second portion of the gate dielectric layer and a second portion of the filling layer. The semiconductor device structure includes a first isolation layer between the first gate structure and the second gate structure, wherein the first isolation layer has an extending portion which is formed in a recess between the gate dielectric layer and the filling layer.

Single gate and dual gate FinFET devices suitable for use in an SRAM memory array have respective fins, source regions, and drain regions that are formed from portions of a single, contiguous layer on the semiconductor substrate, so that STI is unnecessary. Pairs of FinFETs can be configured as dependent-gate devices wherein adjacent channels are controlled by a common gate, or as independent-gate devices wherein one channel is controlled by two gates. Metal interconnects coupling a plurality of the FinFET devices are made of a same material as the gate electrodes. Such structural and material commonalities help to reduce costs of manufacturing high-density memory arrays.

A method includes forming a first fin and a second fin over a substrate. The method includes forming a first dummy gate structure that straddles the first fin and the second fin. The first dummy gate structure includes a first dummy gate dielectric and a first dummy gate disposed over the first dummy gate dielectric. The method includes replacing a portion of the first dummy gate with a gate isolation structure. The portion of the first dummy gate is disposed over the second fin. The method includes removing the first dummy gate. The method includes removing a first portion of the first dummy gate dielectric around the first fin, while leaving a second portion of the first dummy gate dielectric around the second fin intact. The method includes forming a gate feature straddling the first fin and the second fin, wherein the gate isolation structure intersects the gate feature.

A semiconductor structure is provided. The semiconductor structure includes a substrate, a front end of line (FEOL) structure, and a metallization structure. The FEOL structure is disposed over the substrate. The metallization structure is over the FEOL structure. The metallization structure includes a transistor structure, an isolation structure, and a capacitor. The transistor structure has a source region and a drain region connected by a channel structure. The isolation structure is over the transistor structure and exposing a portion of the source region, and a side of the isolation structure has at least a lateral recess vertically overlaps the channel structure. The capacitor is in contact with the source region and disposed conformal to the lateral recess. A method for manufacturing a semiconductor structure is also provided.

A semiconductor structure including a semiconductor substrate and at least one patterned dielectric layer is provided. The semiconductor substrate includes a semiconductor portion, at least one first device, at least one second device and at least one first dummy ring. The at least one first device is disposed on a first region surrounded by the semiconductor portion. The at least one second device and the at least one first dummy ring are disposed on a second region, and the second region surrounds the first region. The at least one patterned dielectric layer covers the semiconductor substrate.