A MOSFET fabricated in a semiconductor substrate, includes: a gate oxide region formed atop the semiconductor substrate; a gate polysilicon region formed on the gate oxide region; a source region of a first doping type formed in the semiconductor substrate and located at a first side of the gate polysilicon region; and a drain region of the first doping type formed in the semiconductor substrate and located at a second side of the gate polysilicon region. The gate polysilicon region has a first sub-region of the first doping type, a second sub-region of the first doping type, and a third sub-region of a second doping type, wherein the first sub-region is laterally adjacent to the source region, the second sub-region is laterally adjacent to the drain region, and the third sub-region is formed laterally between the first and second sub-regions.

In an embodiment, a transistor device comprises a semiconductor body comprising a plurality of transistor cells comprising a drift region of a first conductivity type, a body region of a second conductivity type forming a first pn junction with the drift region, the second conductivity type opposing the first conductivity type, a source region of the first conductivity type forming a second pn junction with the body region, a columnar field plate trench extending into a major surface of a semiconductor body and comprising a columnar field plate and a gate trench structure extending into the major surface of the semiconductor body and comprising a gate electrode. At least one of the depth and doping level of the body region locally varies within the transistor cell to improve VGSTH homogeneity within the transistor cell.

The present disclosure relates to: a MOSFET device which is applicable to a semiconductor device and, particularly, is manufactured using silicon carbide; and a manufacturing method therefor. The present disclosure provides a metal-oxide-semiconductor field effect transistor device which may comprise: a drain electrode; a substrate disposed on the drain electrode; an N-type drift layer disposed on the substrate; a plurality of P-type well layer regions disposed on the drift layer and spaced apart from each other to define a channel; an N+ region disposed on the well layer regions and adjacent to the channel; a P+ region disposed at the other side of the channel; a gate oxide layer disposed on the drift layer; a gate layer disposed on the gate oxide layer; and a source electrode disposed on the gate layer.

A method (of generating a layout diagram, the layout diagram being stored on a non-transitory computer-readable medium) includes: selecting first and second standard cells from a standard-cell-library; the first and second standard cells having corresponding first and second heights that are different from each other; stacking the first standard cell on the second standard cell to form a third cell; and including the third cell in a layout diagram. At least one aspect of the method is executed by a processor of a computer.

This application provides a cell structure and its related semiconductor device. Said cell structure includes a semiconductor substrate. In said semiconductor substrate, there are a plurality of first and second trench units. A carrier barrier region and an electric field shielding region corresponding to the first and second trench units are provided at a bottom of each trench. Conductive materials are provided in the trenches to correspondingly form two gate regions. A source-body region is provided between adjacent first trench units and in contact with a first metal layer on a top portion of the semiconductor substrate. A floating region is provided between the first and second trench units and is isolated from a second metal layer by an insulating dielectric. More than one source region is provided in the surface of the source-body region close to a side edge of at least one of the first trench units and the second trench units. A first semiconductor region and the second metal layer in contact with the first semiconductor region are provided at a bottom portion of the semiconductor substrate. This application improves the offset tolerance of the trench etching window through the design of the floating region, to stabilize the gate control performance after the device is fabricated.

The present invention discloses a high-threshold power semiconductor device and a manufacturing method thereof. The high-threshold power semiconductor device includes, in sequence from bottom to top: a metal drain electrode, a substrate, a buffer layer, and a drift region; further including: a composite column body which is jointly formed by a drift region protrusion, a columnar p-region and a columnar n-region on the drift region, a channel layer, a passivation layer, a dielectric layer, a heavily doped semiconductor layer, a metal gate electrode and a source metal electrode. The composite column body is formed by sequentially depositing a p-type semiconductor layer and an n-type semiconductor layer on the drift region and then etching same. The channel layer and the passivation layer are formed in sequence by deposition. Thus, the above devices are divided into a cell region and a terminal region. The dielectric layer, the heavily doped semiconductor layer, the metal gate electrode and the source metal electrode only exist in the cell region, and the passivation layer of the terminal region extends upwards and is wrapped outside the channel layer. This structure can increase a threshold voltage of the device, improve the blocking characteristics of the device and reduce the size of a gate capacitance.

A semiconductor device and a method of manufacturing the semiconductor device to achieve both of a high breakdown voltage and a low on resistance are provided. A semiconductor substrate includes a convex portion protruding upward from a surface of the semiconductor substrate. An n-type drift region is arranged on the semiconductor substrate so as to be positioned between a gate electrode and an n.sup.+-type drain region in plan view, and has an impurity concentration lower than an impurity concentration of the n.sup.+-type drain region. A p-type resurf region is arranged in the convex portion and forms a pn junction with the n-type drift region.

Structures for a laterally-diffused metal-oxide-semiconductor device and methods of forming a structure for a laterally-diffused metal-oxide-semiconductor device. The structure includes a drift well in a semiconductor substrate, source and drain regions in the semiconductor substrate, a gate dielectric layer on the semiconductor substrate, and a buffer dielectric layer on the semiconductor substrate over the drift well. The buffer dielectric layer includes a first side edge adjacent to the drain region, a second side edge adjacent to the gate dielectric layer, a first section extending from the second side edge to the first side edge, and a plurality of second sections extending from the second side edge toward the first side edge. The first section has a first thickness, and the second sections have a second thickness less than the first thickness. A gate electrode includes respective portions that overlap with the buffer dielectric layer and with the gate dielectric layer.

A silicon carbide MOSFET device that includes a silicon carbide substrate of a first dopant type; a first silicon carbide layer of the first dopant type on top of the silicon carbide substrate; a second silicon carbide layer of a second dopant type embedded in a top portion of the first silicon carbide layer; a third silicon carbide layer of the first dopant type embedded in a top portion of the second silicon carbide layer; a gate oxide layer overlapped to the first silicon carbide layer, the second silicon carbide layer and the third silicon carbide layer; and a fourth silicon carbide layer at least partially overlapping with the second silicon carbide layer along a direction normal to the silicon carbide substrate. The first silicon carbide layer has lower doping than the silicon carbide substrate and defines a drift region. The third silicon carbide layer has higher doping than the first silicon carbide layer. The third silicon carbide layer includes a plurality of third portions that run substantially along a first direction. The second silicon carbide layer includes a plurality of second portions that run substantially along the first direction. The fourth silicon carbide layer includes a plurality of fourth portions that run substantially along a second direction perpendicular to the first direction. The first and second directions each is parallel to the silicon carbide substrate. The transversely arranged P+ regions to N+ regions in some embodiments allow adequate P+ area to achieve good body diode performance and protection to the gate oxide, but without consuming significant area of the MOSFET cell.

There is provided a semiconductor device including: an n-type semiconductor substrate having a first main surface and a second main surface on an opposite side of the first main surface; an n-type semiconductor layer arranged on the first main surface of the semiconductor substrate; a pair of trenches formed at a distance from each other on a surface of the semiconductor layer on an opposite side of the semiconductor substrate; a pair of gate electrodes buried in the pair of trenches; a gate insulating film interposed between the gate electrodes and the semiconductor layer; a source electrode formed on the surface of the semiconductor layer on the opposite side of the semiconductor substrate; and a drain electrode formed on the second main surface of the semiconductor substrate.