A RC-IGBT with fast recovery integrated diode is proposed adopting the concept of a hybrid structure with conventional IGBT emitter trench-stop, separated from an embedded low efficiency injection anode diode. The body region of the IGBT and the anode region of the diode are separately patterned and doped, and the metal barrier layer is removed from the diode area allowing a direct ohmic contact of AlSi alloy on the underneath P-doped anode. A full-anode contact opening is present in the diode area. Moreover, corresponding dummy trenches in the diode area are short-circuited to the emitter electrode giving the benefit to reduce the transfer Miller capacitance. In this way, a good trade-off of VF vs Err can be obtained for the integrated diode without downgrading the IGBT performances both in terms of VCEsat and leakage, differently from the case of devices manufactured by lifetime control techniques.

A semiconductor device includes a semiconductor chip having a principal surface, a first-conductivity-type drift region, a second-conductivity-type body region, a first-conductivity-type source region, a plurality of trench source structures that are formed at the principal surface so as to cross the source region and the body region and so as to reach the drift region and that are arranged with intervals therebetween in a first direction, a second-conductivity-type body connection region formed in a region between two of the trench source structures that are adjacent in the surface layer portion of the body region so as to be electrically connected to the body region, and a first-conductivity-type source connection region formed in a region between two of the trench source structures that are adjacent in a region differing from the body connection region in the surface layer portion of body region so as to be electrically connected to source region.

A semiconductor device includes a first MOS structure portion that includes, as its elements, a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, a first second-semiconductor-layer of a second conductivity type, first semiconductor regions of the first conductivity type, and first gate insulating films, and a second MOS structure portion that includes, as its elements, the substrate, the first semiconductor layer, a second second-semiconductor-layer, second first-semiconductor-regions of the first conductivity type, and second gate insulating films. First and second portions include all of the elements of the first and second MOS structure portions other than the first and second first-semiconductor-regions and the first and second gate insulating films, respectively. A structure of one of the elements of the first portion is not identical to a structure of a corresponding element of the second portion.

Provided is a first vertical field effect transistor in which first source regions and first connection portions via which a first body region is connected to a first source electrode are disposed alternately and cyclically in a first direction in which first trenches extend. In a second direction orthogonal to the first direction, Lxm≤Lxr≤0.20 μm holds true where Lxm denotes a distance between adjacent first trenches and Lxr denotes the inner width of a first trench. The lengths of the first connection portions are in a convergence region in which the on-resistance of the vertical field effect transistor at the time when a voltage having a specification value is applied to first gate conductors to supply current having a specification value does not decrease noticeably even when the lengths of the first connection portions are made much shorter.

A vertical power semiconductor device includes a semiconductor body having opposing first and second main surfaces. At least part of a gate trench structure formed at the first main surface extends along a first lateral direction. Body and source regions directly adjoin the gate trench structure. A drift region is arranged between the body region and second main surface. A body contact structure includes first and second body contact sub-regions spaced at a first lateral distance along the first lateral direction. Each body contact sub-region directly adjoins the gate trench structure and has a larger doping concentration than the body region. In a channel region between the body contact sub-regions, the body contact structure has a second lateral distance to the gate trench structure along a second lateral direction perpendicular to the first lateral direction. The first lateral distance is equal to or less than twice the second lateral distance.

A semiconductor device includes a cell. The cell includes an active area, gates, at least one gate via and at least one contact via. The active area includes forbidden regions. The gates are disposed across the active area. The at least one gate via is coupled with one of the gates. The at least one contact via is coupled with at least one conductive segment each corresponding to a source/drain of a transistor. In a layout view, one of the forbidden regions abuts a region of an abutted cell in which at least one of a gate via or a contact via of the abutted cell is disposed. In a layout view, the least one of the at least one gate via or the at least one contact via is arranged within the active area and outside of the forbidden regions. A method is also disclosed herein.

Provided is a semiconductor device comprising an active region and an edge region, the semiconductor device comprising: a drift region of a first conductivity type provided in the semiconductor substrate; a base region of a second conductivity type provided above the drift region; a first collector region of the second conductivity type provided below the drift region in the active region; and a second collector region of the second conductivity type provided below the drift region in the edge region, wherein a doping concentration of the first collector region is higher than a doping concentration of the second collector region, wherein an area of the first collector region is of the same size as an area of the second collector region or larger than the area of the second collector region, in a top plan view.

A semiconductor device includes a substrate having a front surface including a first long side and a second long side extending in a first direction and opposed to each other, and a first short side and a second short side extending in a second direction intersecting the first direction and opposed to each other, a source finger provided on the front surface, a drain finger provided on the front surface, and a gate finger provided on the front surface and sandwiched between the source finger and the drain finger, wherein a via hole penetrating the substrate is provided in the substrate, a region where the via hole is connected to the source finger in the front surface is contained within the source finger, and the via hole has a maximum width in the first direction larger than a maximum width in the second direction.

A semiconductor substrate has a transistor region, a diode region, and an outer peripheral region. The transistor region is divided into a plurality of transistor unit cell regions by a plurality of gate electrodes each having a stripe shape, and the diode region is divided into a plurality of diode unit cell regions by the plurality of gate electrodes. Each of the plurality of transistor unit cell regions has a third semiconductor layer of a first conductivity type provided on a first main surface side of the semiconductor substrate, a fourth semiconductor layer of a second conductivity type selectively provided on an upper layer part of the third semiconductor layer, and a fifth semiconductor layer. The fifth semiconductor layer is provided to be in contact with an impurity layer of the first conductivity type provided in the outer peripheral region, or to enter the impurity layer.

A power semiconductor device includes an active region with power cells, each configured to conduct a load current portion between first and second load terminals. Each power cell includes: trenches and mesas laterally confined by the trenches and in a vertical direction adjoining a drift region. The mesas include an active mesa having a source region of a first conductivity type and a body region of a second conductivity type separating the source region from the drift region. Both the source and body region are electrically connected to the first load terminal. At least one trench adjacent to the active mesa is configured to induce a conductive channel in the active mesa. A punch through structure s electrically separated from the active mesa by at least one separation stack.