A power semiconductor device includes a semiconductor layer, a ladder-shaped trench recessed a specific depth from a surface of the semiconductor layer into the semiconductor layer and including a pair of lines having a first depth and a plurality of connectors connected between the pair of lines and having a second depth shallower than the first depth, a well region defined in the semiconductor layer between the pair of lines and between the plurality of connectors of the trench, a floating region defined in the semiconductor layer outside the pair of lines of the trench, a gate insulating layer disposed on an inner wall of the trench, and a gate electrode layer disposed on the gate insulating layer to fill the trench and including a first portion in which the pair of lines is filled and a second portion in which the plurality of connectors is filled. A depth of the second portion of the gate electrode layer is shallower than a depth of the first portion of the gate electrode layer.

A main semiconductor device element has first and second p.sup.+-type high-concentration regions that mitigate electric field applied to bottoms of trenches. The first p.sup.+-type high-concentration regions are provided separate from p-type base regions, face the bottoms of the trenches in a depth direction, and extend in a linear shape in a first direction that is a same direction in which the trenches extend. Between adjacent trenches of the trenches, the second p.sup.+-type high-concentration regions are provided scattered in the first direction, separate from the first p.sup.+-type high-concentration regions and the trenches and in contact with the p-type base regions. Between the second p.sup.+-type high-concentration regions adjacent to one another in the first direction, n-type current spreading regions or n.sup.+-type high-concentration regions having an impurity concentration higher than that of the n-type current spreading regions are provided in contact with the second p.sup.+-type high-concentration regions.

The source region, drain region, buried insulating film, gate insulating film, and gate electrode of the semiconductor device are formed in a main surface of a semiconductor substrate. The buried insulating film is buried in a first trench formed between the source and drain regions. The first trench has a first side surface and a first bottom surface. The first side surface faces the source region in a first direction extending from one of the source and drain regions to the other. The first bottom surface is connected to the first side surface and is along the main surface of the semiconductor substrate. A crystal plane of a first surface of the semiconductor substrate, which is the first side surface of the first trench, is (111) plane. A crystal plane of a second surface of the semiconductor substrate, which is the bottom surface of the first trench, is (100) plane.

All of four of built-in gate resistance trenches function as practical built-in gate resistance trenches. A first end portion of each of four of the built-in gate resistance trenches is electrically connected to a wiring side contact region of a gate wiring via a wiring contact. A second end portion of each of four of the built-in gate resistance trenches is electrically connected to a pad side contact region of a gate pad via a pad contact. In each of four of the built-in gate resistance trenches, a distance between the wiring contact and the pad contact is defined as an inter-contact distance.

Provided is a semiconductor device including: a semiconductor substrate provided with an active portion and an edge termination structure portion surrounding the active portion; an interlayer dielectric film provided above the semiconductor substrate; a protective film provided above the interlayer dielectric film; and a protruding portion provided farther from the active portion than the edge termination structure portion and protruding further than the interlayer dielectric film. The protruding portion is not covered with the protective film. The protective film is provided closer to the active portion than the protruding portion.

A semiconductor device that achieves both miniaturization and high breakdown voltage is disclosed. The semiconductor device has a gate electrode G1 formed in a trench TR extending in Y direction and a plurality of column regions PC including column regions PC1 to PC3 formed in a drift region ND. The column regions PC1, PC2 and PC3 are provided in a staggered manner to sandwich the trench TR. An angle θ1 formed by a line connecting the centers of the column regions PC1 and PC2 and a line connecting the centers of the column regions PC1 and PC3 is 60 degrees or more and 90 degrees or less.

A Field Effect Transistor (FET) may include a semiconductor substrate having a first conductivity type, a semiconductor layer of the first conductivity type formed over the substrate, and a pair of doped bodies of a second conductivity type opposite the first conductivity type formed in the semiconductor layer. A trench filled with a trench dielectric is formed within a region between the doped bodies. The FET may be a Vertical Metal-Oxide-Semiconductor FET (VMOSFET) including a gate dielectric disposed over the region between the doped bodies and the trench, and a gate electrode disposed over the gate dielectric, wherein the trench operates to prevent breakdown of the gate dielectric, or the FET may be a Junction FET. The FET may be designed to operate at radio frequencies or under heavy-ion bombardment. The semiconductor substrate and the semiconductor layer may comprise a wide band-gap semiconductor such as silicon carbide.

A semiconductor device has a cell region, a dividing region dividing the cell region in an expanding direction of a stacking fault band, and a termination region, and includes in a dividing region, a semiconductor layer including a drift region of a first conductivity type and a second well region of a second conductivity type provided in an upper portion of the drift region, a second interlayer insulating film provided on the semiconductor layer, and a source electrode provided on the second interlayer insulating film. The second interlayer insulating film has two second contact holes aligned in an expanding direction of stacking fault band and electrically connecting the source electrode to the second well region. The second well region is formed as one region continuous in the expanding direction of stacking fault band in the region interposed between the two second contact holes in top view.

A semiconductor device includes a semiconductor part, a first electrode at a back surface of the semiconductor part; a second electrode at a front surface of the semiconductor part; third and fourth electrodes provided between the semiconductor part and the second electrode. The third and fourth electrodes are arranged in a first direction along the front surface of the semiconductor part. The third electrode is electrically insulated from the semiconductor part by a first insulating film. The third electrode is electrically insulated from the second electrode by a second insulating film. The fourth electrode is electrically insulated from the semiconductor part by a third insulating film. The fourth electrode is electrically isolated from the third electrode. the third and fourth electrodes extend into the semiconductor part. The fourth electrode includes a material having a larger thermal conductivity than a thermal conductivity of a material of the third electrode.

A semiconductor device includes a semiconductor layer structure of a wide band-gap semiconductor material. The semiconductor layer structure includes a drift region having a first conductivity type and a well region having a second conductivity type. A plurality of segmented gate trenches extend in a first direction in the semiconductor layer structure. The segmented gate trenches include respective gate trench segments that are spaced apart from each other in the first direction with intervening regions of the semiconductor layer structure therebetween. Related devices and fabrication methods are also discussed.