The present disclosure relates to a semiconductor structure and a manufacturing process therefor. Provided is a method for manufacturing a bipolar transistor with a trench structure, including providing a semiconductor substrate; fabricating a shallow trench isolation structure to define a device active area; forming an N-type well and a P-type well in the active area to define a first region, a second region and a third region of the bipolar transistor; etching a portion, adjacent to the shallow trench isolation structure, in the first region to form a trench; performing ion implantation to form an emitter, a base and a collector of the bipolar transistor; forming a salicide block structure in the trench; and forming a metal electrode of the bipolar transistor, wherein the emitter is formed in the first region. The present disclosure further provides a bipolar transistor with a trench structure.

A transistor includes a substrate of a first conductivity type. An epitaxial layer of the first conductivity type is formed at a top surface of the substrate. A first region of the first conductivity type is formed as a well in the epitaxial layer. A second region of a second conductivity type is formed as a well in the epitaxial layer adjacent to the first region and the second conductivity type is opposite of the first conductivity type. A third region of the second conductivity type is formed in the first region and a portion of the first region forms a channel region between the third region and the second region. An emitter region of the first conductivity type is formed in the second region. A gate dielectric is formed over the channel region, and a gate electrode is formed on gate dielectric with the gate electrode overlapping at least a portion of second region and the third region.

A structure and method of forming a lateral bipolar junction transistor (LBJT) that includes: a first base layer, a second base layer over the first base layer, and an emitter region and collector region present on opposing sides of the first base layer, where the first base layer has a wider-band gap than the second base layer, and where the first base layer includes a III-V semiconductor material.

An electrostatic discharge protection structure includes a semiconductor substrate and a first n-type well region, a p-type well region, a first p-type doped region, a second p-type doped region, and an isolation structure disposed in the semiconductor substrate. The p-type well region is located adjacent to the first n-type well region. The first p-type doped region and the second p-type doped region are located above the first n-type well region and the p-type well region, respectively. A first portion of the isolation structure is located between the first p-type doped region and the second p-type doped region in a horizontal direction. An edge of the first n-type well region is located under the first portion. A distance between the first p-type doped region and the edge of the first n-type well region in the horizontal direction is less than a length of the first portion in the horizontal direction.

A semiconductor device includes first to fifth regions, first and second resistive loads. The first region is coupled to a first reference voltage terminal. The first to third regions operate as a first transistor. The fourth region is coupled to a second reference voltage terminal. The fourth to fifth regions operate as a second transistor. The first resistive load couples the second region to the second reference voltage terminal. The second resistive load couples the fifth region to the first reference voltage terminal. The first, third, second, fifth and fourth regions are arranged in order, each of the first, second and third regions corresponds to a first conductive type, and each of the fourth and fifth regions corresponds to a second conductive type.

A bipolar junction transistor includes a semiconductor substrate, a fin structure, an epitaxial emitter, an epitaxial collector and a gate. The fin structure is disposed on the semiconductor substrate and has a base portion of a first conductivity type, a first recessed portion and a second recessed portion. The epitaxial emitter of a second conductivity type is disposed in the first recessed portion of the fin structure. The epitaxial collector of the second conductivity type is disposed in the second recessed portion of the fin structure. The gate is disposed on the base portion of the fin structure and isolated from the base portion of the fin structure.

A method for fabricating bipolar junction transistor (BJT) includes the steps of: providing a substrate having an emitter region, a base region, and a collector region; performing a first implantation process to form a first well region in the base region; and performing a second implantation process to form a second well region in the emitter region. Preferably, the first well region and the second well region comprise different concentration.

A method of fabricating a semiconductor device comprises forming, within a single process flow on a silicon on insulator (SOI) wafer, at least one of an n channel, digital VeSFET, a p channel, digital VeSFET, an n channel, analog VeSFET and a p channel, analog VeSFET. The method may further comprise forming, on the SOI wafer, at least one of a JFET, a BJT and a LT-MOM capacitor. The method may further comprise forming the n channel, digital VeSFET, a p channel, digital VeSFET, an n channel, analog VeSFET, and a p channel, analog VeSFET, according to a periodic design based on a unit circle. The method may comprise modifying a design of the semiconductor node, according to a three-dimensional architecture, to form a modified semiconductor node, and fabricating the modified semiconductor node on substrate, along with at least one other node of a different node type.

A symmetrical lateral bipolar junction transistor (SLBJT) is provided. The SLBJT includes a p-type semiconductor substrate, a n-type well, an emitter of a SLBJT situated in the n-type well, a base of the SLBJT situated in the n-type well and spaced from the emitter by a distance on one side of the base, a collector of the SLBJT situated in the n-type well and spaced from the base by the distance on an opposite side of the base, and an electrical connection to the substrate outside the n-type well. The SLBJT is used to characterize a transistor in a circuit by electrically coupling the SLBJT to a gate of the test transistor, applying a voltage to the gate, and characterizing aspect(s) of the test transistor under the applied voltage. The SLBJT protects the gate against damage to the gate dielectric.

A device comprises a high voltage n well and a high voltage p well over a buried layer, a first low voltage n well over the high voltage n well, wherein a bottom portion of the first low voltage n well is surrounded by the high voltage n well, an N+ region over the first low voltage n well, a second low voltage n well and a low voltage p well over the high voltage p well, a first P+ region over the second low voltage n well and a second P+ region over the low voltage p well.