A collector layer, a base layer, and an emitter layer that are disposed on a substrate form a bipolar transistor. An emitter electrode is in ohmic contact with the emitter layer. The emitter layer has a shape that is long in one direction in plan view. A difference in dimension with respect to a longitudinal direction of the emitter layer between the emitter layer and an ohmic contact interface at which the emitter layer and the emitter electrode are in ohmic contact with each other is larger than a difference in dimension with respect to a width direction of the emitter layer between the emitter layer and the ohmic contact interface.

A semiconductor device includes an HBT; emitter wiring which is connected to an emitter electrode of the HBT and covers the HBT; a passivation film having an opening on the HBT in plan view; a UBM layer which is connected to the emitter wiring through the opening and made of a refractory metal with a thickness of 300 nm or more; and a pillar bump which is arranged on the UBM layer and includes a metal post and a solder layer. The UBM layer serves as a stress relaxation layer, thereby relaxing stress on the HBT due to a difference in thermal expansion coefficient between a GaAs-based material of each layer constituting the HBT and the pillar bump.

A method of making a bipolar transistor includes forming a stack of a first, second, third and fourth insulating layers on a substrate. An opening is formed in the stack to reach the substrate. An epitaxial process forms the collector of the transistor on the substrate and selectively etches an annular opening in the third layer. The intrinsic part of the base is then formed by epitaxy on the collector, with the intrinsic part being separated from the third layer by the annular opening. The junction between the collector and the intrinsic part of the base is surrounded by the second layer. The emitter is formed on the intrinsic part and the third layer is removed. A selective deposition of a semiconductor layer on the second layer and in direct contact with the intrinsic part forms the extrinsic part of the base.

A bipolar junction transistor is provided with a multilayer collector structure. The layers of the collector are individually grown in separate epitaxial growth stages. For a PNP transistor, each layer, after it is grown, is doped with a p-type dopant in a dedicated implant stage. By providing separate epitaxial growth stages and separate dopant implant stages for each layer of the collector, the dopant concentration profile in the collector region can be better controlled to optimize the speed and breakdown voltage of a bipolar junction transistor.

A memory device, and a method of making the same, includes a resistive random-access memory element electrically connected to an extrinsic base region of a bipolar junction transistor, the extrinsic base region of the bipolar junction transistor consisting of an epitaxially grown material that forms the bottom electrode of the resistive random-access memory element. Additionally, a method of writing to the memory device includes applying a first voltage on a word line of the memory device to form a filament in the resistive random-access memory element. A second voltage including an opposite polarity to the first voltage can be applied to the word line to remove a portion of the filament in the resistive random-access memory element.

Aspects of the disclosure provide an integrated circuit (IC) structure with a bipolar transistor stack within a substrate. The bipolar transistor stack may include: a collector, a base on the collector, and an emitter on a first portion of the base. A horizontal width of the emitter is less than a horizontal width of the base, and an upper surface of the emitter is substantially coplanar with an upper surface of the substrate. An extrinsic base structure is on a second portion of the base of the bipolar transistor stack, and horizontally adjacent the emitter. The extrinsic base structure includes an upper surface above the upper surface of the substrate.

A heterojunction bipolar transistor, comprising: a substrate, having a first surface and an opposite second surface; a sub-emitter layer arranged on the first surface; a compound emitter layer arranged on the sub-emitter layer, making the sub-emitter layer and the compound emitter layer forms an emitter layer; a base layer arranged on the compound emitter layer; a collector ledge layer arranged on the base layer; a collector layer arranged on the collector ledge layer; a lateral oxidation region arranged on the compound emitter layer forming a current blocking region, and the outer region of the compound emitter layer surrounds inner region, so that the inner region of the compound emitter layer forms a current aperture.

Disclosed is a transistor having a base, a substrate, and a collector between the substrate and the base. The collector has a first region of a first thickness under the base and is made up of a first dopant type having a substantially constant doping concentration across the first thickness. A second region with a second thickness under the first region is made up of a second dopant type that is different from the first dopant type and has a substantially constant doping concentration across the second thickness. A third region with a third thickness under the second region is made up of the second dopant type with a graded doping concentration that is a function of increasing distance from the second region through the third thickness. An emitter is located over the base opposite the collector.

A heterojunction bipolar transistor may include a base epitaxially grown on a collector, an emitter epitaxially grown on the base, the emitter and the base being patterned into a fin, and a silicon oxide layer formed on sidewalls of the fin, the silicon oxide layer separating the base from a spacer. The heterojunction bipolar transistor may include the spacer formed on top of the silicon oxide layer and an interlayer dielectric formed on top of the spacer. The heterojunction bipolar transistor may also include a silicon germanium oxide layer formed on sidewalls of the base. The base may be made of silicon germanium. The emitter and the collector may be made of silicon. The base may be doped with a p-type dopant. The emitter and the collector may be doped with a n-type dopant.

The present invention provides a heterojunction bipolar transistor and a method of making the same, applying fin replacement technology, fins are formed on a substrate, a well region served as a collector region is formed in the substrate, and a bottom of the fins connects to the well region served as the collector. A first part of the well region corresponding to the fin is removed, i.e. hollow a part of the fins out to form a first opening, and material of a base region is then deposited to form a fin base. A remaining part of the fin corresponding to the well region is removed, i.e. hollow the remaining part of the fins out to form a second opening, and the base region is then deposited. Then, on the base region, an emitter region is formed. A base region epitaxy cap layer and an emitter region epitaxy cap layer are formed outside the fin base and the emitter region respectively. Above-mentioned method may be integrated to the FinFET technology platform. As such, in the present invention, equivalent base and resistances of the collector electrode of the heterojunction bipolar transistor are less, leakage current of the transistor is low, electrical performance is great, and integration with a FinFET device is easier to promote integration density of the device.