A semiconductor device includes a single semiconductor substrate on which an IGBT region including an IGBT element and an FWD region including a FWD element are formed. In the semiconductor device, a cathode layer is formed with a carrier injection layer, which is electrically connected to a second electrode and has a PN junction with a field stop layer. When a first carrier in the FWD element passes through the field stop layer on the carrier injection layer and flows into the cathode layer in a situation where a forward-biased current is cut off from a state in which the forward-biased current is flowing through the FWD element, a second carrier is injected from the second electrode into a drift layer through the carrier injection layer.

An electrically conductive sub-collector layer is provided in a surface layer portion of a substrate. A collector layer, a base layer, and an emitter layer are located within the sub-collector layer when viewed in plan. The collector layer is connected to the sub-collector layer. An emitter electrode and a base electrode are long in a first direction when viewed in plan. The emitter electrode overlaps the emitter layer. The base electrode and the emitter electrode are discretely located away from each other in a second direction orthogonal to the first direction. A collector electrode is located on one side in the second direction with respect to the emitter electrode and is not located on the other side when viewed in plan. A base line is connected to the base electrode in a manner so as to adjoin a portion other than longitudinal ends of the base electrode.

A bipolar transistor includes a collector layer, a base layer, and an emitter layer that are formed in this order on a compound semiconductor substrate. The emitter layer is disposed inside an edge of the base layer in plan view. A base electrode is disposed on partial regions of the emitter layer and the base layer so as to extend from an inside of the emitter layer to an outside of the base layer in plan view. An insulating film is disposed between the base electrode and a portion of the base layer, with the portion not overlapping the emitter layer. An alloy layer extends from the base electrode through the emitter layer in a thickness direction and reaches the base layer. The alloy layer contains at least one element constituting the base electrode and elements constituting the emitter layer and the base layer.

One aspect of this disclosure is a power amplifier module that includes a power amplifier, a semiconductor resistor, a tantalum nitride terminated through wafer via, and a conductive layer electrically connected to the power amplifier. The semiconductor resistor can include a resistive layer that includes a same material as a layer of a bipolar transistor of the power amplifier. A portion of the conductive layer can be in the tantalum nitride terminated through wafer via. The conductive layer and the power amplifier can be on opposing sides of a semiconductor substrate. Other embodiments of the module are provided along with related methods and components thereof.

At least one transistor is arranged on a substrate. A collector layer and a base layer of the transistor compose a collector mesa having a substantially mesa shape and the collector mesa has side faces tilting with respect to the substrate so that the dimension of a top face in a first direction of a plane of the substrate is smaller than the dimension of a bottom face therein. A first insulating film covering the transistor is arranged on the substrate. A first-layer emitter line that extends from an area overlapped with the top face of the collector mesa to areas overlapped with at least part of the tilting side faces of the collector mesa in a plan view is arranged on the first insulating film. A second-layer emitter line and an emitter bump are arranged on the first-layer emitter line.

A collector layer is disposed on a substrate. The collector layer is a continuous region when viewed in plan. A base layer is disposed on the collector layer. An emitter layer is disposed on the base layer. An emitter mesa layer is disposed on the emitter layer. Two base electrodes are located outside the emitter mesa layer and within the base layer when viewed in plan. The two base electrodes are electrically connected to the base layer. Two capacitors are disposed on or above the substrate. Each of the two capacitors is connected between a corresponding one of the two base electrodes and a first line above the substrate. Two resistance elements are disposed on or above the substrate. Each of the two resistance elements is connected between a corresponding one of the two base electrodes and a second line on or above the substrate.

One aspect of this disclosure is a power amplifier system that includes a control interface, a power amplifier, a passive component, and a bias circuit. The power amplifier and the passive component can be on a first die. The bias circuit can be on a second die. The control interface can operate as a serial interface or as a general purpose input/output interface. The power amplifier can be controllable based at least partly on an output signal from the control interface. The bias circuit can generate a bias signal based at least partly on an indication of the electrical property of the passive component. Other embodiments of the system are provided along with related methods and components thereof.

At least one transistor is arranged on a substrate. A collector layer and a base layer of the transistor compose a collector mesa having a substantially mesa shape and the collector mesa has side faces tilting with respect to the substrate so that the dimension of a top face in a first direction of a plane of the substrate is smaller than the dimension of a bottom face therein. A first insulating film covering the transistor is arranged on the substrate. A first-layer emitter line that extends from an area overlapped with the top face of the collector mesa to areas overlapped with at least part of the tilting side faces of the collector mesa in a plan view is arranged on the first insulating film. A second-layer emitter line and an emitter bump are arranged on the first-layer emitter line.

A first sub-collector layer functions as an inflow path of a collector current that flows in a collector layer of a heterojunction bipolar transistor. A collector ballast resistor layer having a lower doping concentration than the first sub-collector layer is disposed between the collector layer and the first sub-collector layer.

An epitaxial structure includes a composite base unit and an emitter unit. The composite base unit includes a first base layer and a second base layer formed on the first base layer. The first base layer is made of a material of In.sub.xGa.sub.(1-x)As.sub.(1-y)N.sub.y, in which 0<x≤0.2, and 0≤y≤0.035, and when y is not 0, x=3y. The second base layer is made of a material In.sub.mGa.sub.(1-m)As, in which 0.03≤m≤0.2. The emitter unit is formed on the second base layer 12 opposite to the first base layer 11, and is made of an indium gallium phosphide-based material. A transistor including the epitaxial structure is also disclosed.