Provided is a semiconductor device comprising: a semiconductor substrate provided with a drift region; a buffer region arranged between the drift region and the lower surface, wherein a doping concentration distribution has three or more concentration peaks; and a collector region arranged between the buffer region and the lower surface, wherein the three or more concentration peaks in the buffer region include: a first concentration peak closest to the lower surface; a second concentration peak closest, next to the first concentration peak, to the lower surface, arranged 5 μm or more distant from the lower surface in the depth direction, and having a doping concentration lower than the first concentration peak, the doping concentration being less than 1.0×10.sup.15/cm.sup.3; and a high concentration peak arranged farther from the lower surface than the second concentration peak, and having a higher doping concentration than the second concentration peak.

Directly beneath p.sup.−-type base regions, n-type storage regions are provided. The storage regions contain hydrogen donors as an impurity and have an impurity concentration higher than that of the n.sup.−-type drift region. The storage regions are formed by hydrogen ion irradiation from a back surface of a semiconductor substrate. The storage regions have a peak hydrogen concentration and are at positions that coincide with where the hydrogen ions have been irradiated. By the hydrogen ion irradiation, a crystal defect region that is a carrier lifetime killer region is formed concurrently with the storage regions, closer to the back surface of the semiconductor substrate than are storage regions. The crystal defect region has a crystal defect density with a peak density at a position closer to the back surface of the semiconductor substrate than are the storage regions. A semiconductor device having such storage regions and a carrier lifetime killer region is enabled.

A semiconductor device includes pads arrayed between a region where a transistor portion or a diode portion is disposed and a first end side on an upper surface of a semiconductor substrate, and a gate runner portion that transfers a gate voltage to the transistor portion. The gate runner portion has a first gate runner disposed passing between the first end side of the semiconductor substrate and at least one of the pads in the top view, and a second gate runner disposed passing between at least one of the pads and the transistor portion in the top view. The transistor portion is also disposed in the inter-pad regions, the gate trench portion disposed in the inter-pad regions is connected to the first gate runner, and the gate trench portion arranged so as to face the second gate runner is connected to the second gate runner.

The present disclosure describes a semiconductor structure that includes a substrate from an undoped semiconductor material and a fin disposed on the substrate. The fin includes a non-polar top surface and two opposing first and second polar sidewall surfaces. The semiconductor structure further includes a polarization layer on the first polar sidewall surface, a doped semiconductor layer on the polarization layer, a dielectric layer on the doped semiconductor layer and on the second polar sidewall surface, and a gate electrode layer on the dielectric layer and the first polarized sidewall surface.

A doping concentration distribution in an accumulation region in a depth direction of a semiconductor substrate has a maximum portion at which a doping concentration reaches a maximum value, an upper gradient portion in which the concentration decreases from the maximum portion to a base region, and a lower gradient portion in which the concentration decreases from the maximum portion to a drift region. When a full width at half maximum determined by setting a depth position of the maximum portion as a range of impurity implantation with reference to a range-full width at half maximum characteristic according to a material of the substrate and a type of impurities contained in the accumulation region is set as a standard full width at half maximum, a full width at half maximum of the distribution in the accumulation region is 2.2 times the standard full width at half maximum or greater.

A semiconductor device that includes transistor and diode regions in one semiconductor substrate achieves favorable tolerance during recovery behaviors of diodes. A semiconductor base includes an n.sup.−-type drift layer in the IGBT and diode regions. In the IGBT region, the semiconductor base includes a p-type base layer formed on the n.sup.−-type drift layer, a p.sup.+-type diffusion layer and an n.sup.+-type emitter layer formed selectively on the p-type base layer, the diffusion layer having a higher p-type impurity concentration than the p-type base layer, and gate electrodes facing the p-type base layer via a gate insulating film. In the diode region, the semiconductor base includes a p.sup.−-type anode layer formed on the n.sup.−-type drift layer. The p.sup.+-type diffusion layer has a higher p-type impurity concentration than the p.sup.−-type anode layer, and has a smaller depth and a lower p-type impurity concentration as approaching the diode region.

A semiconductor switching module includes an insulated gate bipolar transistor and a unipolar switching device. The insulated gate bipolar transistor includes a first transistor cell and a supplemental cell, wherein the first transistor cell includes a first gate and a first source and wherein the supplemental cell includes a second gate and a supplemental electrode. The unipolar switching device is based on a wide bandgap material and includes a third gate and a third source. The third gate and the second gate are electrically connected with each other and are disconnected from the first gate. The first source, the supplemental cell and the third source are electrically connected with each other.

A semiconductor device wherein a hydrogen concentration distribution has a first hydrogen concentration peak and a second hydrogen concentration peak and a donor concentration distribution has a first donor concentration peak and a second donor concentration peak in a depth direction, wherein the first hydrogen concentration peak and the first donor concentration peak are placed at a first depth and the second hydrogen concentration peak and the second donor concentration peak are placed at a second depth deeper than the first depth relative to the lower surface is provided.

A semiconductor die with high-voltage tolerant electrical overstress circuit architecture is disclosed. One embodiment of the semiconductor die includes a signal pad, a ground pad, a core circuit electrically connected to the signal pad, and a stacked thyristor protection device. The stacked thyristor includes a first thyristor and a resistive thyristor electrically connected in a stack between the signal pad and the ground pad, which enhances the holding voltage of the circuit relatively to an implementation with only the thyristor. Further, the resistive thyristor includes a PNP bipolar transistor and a NPN bipolar transistor that are cross-coupled, and an electrical connection between a collector of the PNP bipolar transistor and a collector of the NPN bipolar transistor. This allows the resistive thyristor to exhibit both thyristor characteristics and resistive characteristics based on a level of current flow.

A semiconductor device includes a semiconductor part, first and second electrodes. The semiconductor part is provided between the first and second electrodes. A method of manufacturing the device includes forming the first electrode covering a back surface of a wafer after the second electrode is formed on a front surface of the wafer; forming a first groove by selectively removing the first electrode; and dividing the wafer by forming a second groove at the front surface side. The wafer includes a region to be the semiconductor part; and the first and second grooves are provided along a periphery of the region. The first groove is in communication with the first groove. The second groove has a width in a direction along the front surface of the wafer, the width of the first groove being narrower than a width of the first groove in the same direction.