There is provided a thyristor having emitter shorts, wherein in an orthogonal projection onto a plane parallel to a first main side, a contact area covered by an electrical contact of a first electrode layer with a first emitter layer and the emitter shorts includes areas in the shape of lanes, in which an area coverage of the emitter shorts is less than the area coverage of emitter shorts in the remaining area of the contact area, wherein the area coverage of the emitter shorts in a specific area is the area covered by the emitter shorts in that specific area relative to the specific area. The thyristor of the invention exhibits a fast turn-on process even without complicated amplifying gate structure.

Silicon controlled rectifiers (SCR), methods of manufacture and design structures are disclosed herein. The method includes forming a common P-well on a buried insulator layer of a silicon on insulator (SOI) wafer. The method further includes forming a plurality of silicon controlled rectifiers (SCR) in the P-well such that N+ diffusion cathodes of each of the plurality of SCRs are coupled together by the common P-well.

An Electro-Static-Discharge (ESD) protection device has a Silicon-Controlled Rectifier (SCR) with a triggering PMOS transistor. The SCR is a PNPN structure with a P+ anode/source within a center N-well, a P-substrate, and an outer N-well that connects to a cathode using N+ well taps. The P+ anode/source is both the source of the triggering PMOS transistor and the anode of the SCR. A trigger circuit drives the gate of the triggering PMOS transistor low, turning it on to charge the P+ drain. Since the P+ drain straddles the well boundary, making physical contact with both the center N-well and the P-substrate, holes flow into the P-substrate. The P+ drain is located near guard rings that suppress latch-up. The holes from the P+ drain flood the region under the guard rings, temporarily weakening their effect and reducing the trigger voltage.

An Electro-Static-Discharge (ESD) protection device has a Silicon-Controlled Rectifier (SCR) with a triggering PMOS transistor. The SCR is a PNPN structure with a P+ anode/source within a center N-well, a P-substrate, and an outer N-well that connects to a cathode using N+ well taps. The P+ anode/source is both the source of the triggering PMOS transistor and the anode of the SCR. A trigger circuit drives the gate of the triggering PMOS transistor low, turning it on to charge the P+ drain. Since the P+ drain straddles the well boundary, making physical contact with both the center N-well and the P-substrate, holes flow into the P-substrate. The P+ drain is located near guard rings that suppress latch-up. The holes from the P+ drain flood the region under the guard rings, temporarily weakening their effect and reducing the trigger voltage.

An insulated gate turn-off (IGTO) device, formed as a die, has a layered structure including a p+ layer (e.g., a substrate), an n epi layer, a p-well, vertical insulated gate regions formed in the p-well, and n+ regions between the gate regions, so that vertical NPN and PNP transistors are formed. The device is formed of a matrix of cells. To turn the device on, a positive voltage is applied to the gate, referenced to the cathode. The cells further contain a vertical p-channel MOSFET, for shorting the base of the NPN transistor to its emitter, to turn the NPN transistor off when the p-channel MOSFET is turned on by a slight negative voltage applied to the gate. This allows the IGTO device to be more easily turned off while in a latch-up condition, when the device is acting like a thyristor.

The present invention relates to a thyristor having a vertical structure and a cross-point memory array including the same. The thyristor having a vertical structure according to one embodiment may include a semiconductor core with an insulating film formed on the outer peripheral surface thereof, and a plurality of metal layers formed on the insulating film. In the semiconductor core, at least one layer of a base layer and an emitter layer may be formed on a region corresponding to each of the metal layers based on the charge plasma phenomenon due to the difference in work function with the metal layers.

An RC-IGBT includes a semiconductor substrate having a cell region, a wiring region, and a termination region. The semiconductor substrate includes a diffusion layer of a second conductivity type provided on a first main surface side of a drift layer in an IGBT region, a diode region, the wiring region, and the termination region. The diffusion layer includes a base layer in the IGBT region, an anode layer in the diode region, a wiring well layer in the wiring region, and a termination well layer in the termination region. A depth of the base layer is less than depths of a plurality of trench gates, and is equal to or more than depths of the anode layer, the wiring well layer, and the termination well layer.

The invention relates to a bipolar non-punch-through power semiconductor device and a corresponding manufacturing method. The device comprises a semiconductor wafer and a first electrode formed on a first main side of the wafer and a second electrode formed on a second main side of the wafer opposite the first main side. The wafer comprises a pair of layers of different conductivity types, such as a drift layer of a first conductivity type, and a first layer of a second conductivity type arranged on the drift layer towards the first main side and contacting the first electrode. The wafer comprises an inner region wand an outer region surrounding the inner region. The drift layer has a thickness in the inner region greater or equal than a thickness in the outer region. A thickness of the first layer increases in a transition region between the inner region and the outer region from a thickness in the inner region to a maximum thickness in the outer region. The thickness of the first layer increases linearly over the transition region with a width of the transition region greater than 5 times a thickness of the first section of the first layer.

SCRs are a must for ESD protection in low voltagehigh speed I/O as well as ESD protection of RF pads due to least parasitic loading and smallest foot print offered by SCRs. However, conventionally designed SCRs in FinFET and Nanowire technology suffer from very high turn-on and holding voltage. This issue becomes more severe in sub-14 nm non-planar technologies and cannot be handled by conventional approaches like diode- or transient-turn-on techniques. Proposed invention discloses SCR concept for FinFET and Nanowire technology with diffused junction profiles with sub-3V trigger and holding voltage for efficient and robust ESD protection. Besides low trigger and holding voltage, the proposed device offers a 3 times better ESD robustness per unit area.

The invention relates to a turn-off power semiconductor device comprising a plurality of thyristor cells, each thyristor cell comprising a cathode region; a base layer; a drift layer; an anode layer; a gate electrode which is arranged lateral to the cathode region in contact with the base layer; a cathode electrode; and an anode electrode. Interfaces between the cathode regions and the cathode electrodes as well as interfaces between the base layers and the gate electrodes of the plurality of thyristor cells are flat and coplanar. In addition, the base layer includes a gate well region extending from its contact with the gate electrode to a depth, which is at least half of the depth of the cathode region, wherein, for any depth, the minimum doping concentration of the gate well region at this depth is 50% above a doping concentration of the base layer between the cathode region and the gate well region at this depth and at a lateral position, which has in an orthogonal projection onto a plane parallel to the first main side a distance of 2 m from the cathode region. The base layer includes a compensated region of the second conductivity type, the compensated region being arranged directly adjacent to the first main side and between the cathode region and the gate well region, wherein the density of first conductivity type impurities relative to the net doping concentration in the compensated region is at least 0.4.