A method includes forming a protruding semiconductor stack including a plurality of sacrificial layers and a plurality of nanostructures, with the plurality of sacrificial layers and the plurality of nanostructures being laid out alternatingly. The method further includes forming a dummy gate structure on the protruding semiconductor stack, etching the protruding semiconductor stack to form a source/drain recess, and forming a source/drain region in the source/drain recess. The formation of the source/drain region includes growing first epitaxial layers. The first epitaxial layers are grown on sidewalls of the plurality of nanostructures, and a cross-section of each of the first epitaxial layers has a quadrilateral shape. The first epitaxial layers have a first dopant concentration. The formation of the source/drain region further includes growing a second epitaxial layer on the first epitaxial layers. The second epitaxial layer has a second dopant concentration higher than the first dopant concentration.

A method for forming a semiconductor structure is provided. The method includes forming a fin structure over a substrate. The fin structure includes a protection layer and alternating first and second semiconductor layers over the protection layer. The method also includes etching the fin structure to form a source/drain recess, forming a sacrificial contact in the source/drain recess, forming a source/drain feature over the sacrificial contact in the source/drain recess, removing the first semiconductor layers of the fin structure, thereby forming a plurality of nanostructures, forming a gate stack wrapping around the nanostructures, removing the substrate thereby exposing the protection layer and the sacrificial contact and replacing the sacrificial contact with a contact plug.

According to example embodiments, an integrated circuit includes a continuous active region extending in a first direction, a tie gate electrode extending in a second direction crossing the first direction on the continuous active region, a source/drain region provided adjacent the tie gate electrode, a tie gate contact extending in a third direction perpendicular to the first direction and the second direction on the continuous active region and connected to the tie gate electrode, a source/drain contact extending in the third direction and connected to the source/drain region, and a wiring pattern connected to each of the tie gate contact and the source/drain contact and extending in a horizontal direction. A positive supply power is applied to the wiring pattern.

A field effect transistor (FET) structure upon a substrate formed by forming a stack of nanosheets upon a semiconductor substrate, the stack including alternating layers of a compound semiconductor material and an elemental semiconductor material, forming a dummy gate structure upon the stack of nanosheets, recessing the stack of nanosheets in alignment with the dummy gate structure, recessing the compound semiconductor layers beyond the edges of the dummy gate, yielding indentations between adjacent semiconductor nanosheets. Further by filling the indentations with a bi-layer dielectric material, epitaxially growing source/drain regions adjacent to the nanosheet stack and bi-layer dielectric material, removing remaining portions of the compound semiconductor nanosheet layers, recessing the bi-layer dielectric material to expose an inner material layer, and forming gate structure layers in contact with first and second dielectric materials of the bi-layer dielectric material.

Disclosed are a semiconductor device and a method of fabricating the same. The device includes an FEOL layer, which includes a plurality of individual devices, on a substrate, and first, second, and third metal layers sequentially stacked on the FEOL layer. The second metal layer includes an interlayer insulating layer and an interconnection line in the interlayer insulating layer. The interconnection line includes a lower via portion electrically connected to the first metal layer, an upper via portion electrically connected to the third metal layer, and a line portion between the lower via portion and the upper via portion. A line width of an upper portion of the interconnection line gradually decreases in a vertical direction away from the substrate, and a line width of a lower portion of the interconnection line gradually increases in a vertical direction away from the substrate.

Techniques herein include methods of forming channel structures for field effect transistors having a channel current path parallel to a surface of a substrate. 3D in-situ horizontal or lateral growth of the channel and source/drain regions allows for a custom doping in the 3D horizontal nanosheet direction for NMOS and PMOS devices. An ultra-short channel length is achieved with techniques herein because the channel is epitaxially grown in the 3D horizontal nanosheet direction at the monolayer level. Since the channel is grown in a dielectric cavity, a precise channel cross sectional area can be tuned.

A 3-dimensional array of NOR memory strings being organized by planes of NOR memory strings, in which (i) the storage transistors in the NOR memory strings situated in a first group of planes are configured to be programmed, erased, program-inhibited or read in parallel, and (ii) the storage transistors in NOR memory strings situated within a second group of planes are configured for storing resource management data relating to data stored in the storage transistors of the NOR memory strings situated within the first group of planes, wherein the storage transistors in NOR memory strings in the second group of planes are configured into sets.

Techniques for recovering the width of a top gate spacer in a field-effect transistor (FET) device are provided. In one aspect, a FET device includes: at least one gate; source/drain regions present on opposite sides of the at least one gate; gate spacers offsetting the at least one gate from the source/drain regions, wherein each of the gate spacers includes an L-shaped spacer alongside the at least one gate and a dielectric liner disposed on the L-shaped spacer; and at least one channel interconnecting the source/drain regions. A method of forming a FET device is also provided which includes recovering the width of the top gate spacer using the dielectric liner.

A method includes depositing a first semiconductor layer and a second semiconductor layer over a substrate; patterning the first semiconductor layer, the second semiconductor layer, and the substrate to form a first nanostructure, a second nanostructure, and a semiconductor fin; forming a recess in the first nanostructure and the second nanostructure, the recess exposing the semiconductor fin; epitaxially growing a first layer in the recess, a first portion of the first layer being disposed along a first sidewall of the first nanostructure, a second portion of the first layer being disposed along the semiconductor fin, the first portion of the first layer comprising two sidewalls extending toward a middle of the recess, the first portion of the first layer further comprising a first surface most distal from the first sidewall and directly interposed between the two sidewalls, the first portion being physically separated from the second portion; and epitaxially growing a second layer over the first portion of the first layer and over the second portion of the first layer, the second layer physically connecting the first portion of the first layer to the second portion of the first layer.

In a method of manufacturing a semiconductor device, a fin structure, which includes a stacked layer of first semiconductor layers and second semiconductor layers disposed over a bottom fin structure and a hard mask layer over the stacked layer, is formed. An isolation insulating layer is formed. A sacrificial cladding layer is formed over at least sidewalls of the exposed hard mask layer and stacked layer. A first dielectric layer is formed. A second dielectric layer is formed over the first dielectric layer. The second dielectric layer is recessed. A third dielectric layer is formed on the recessed second dielectric layer. The third dielectric layer is partially removed to form a trench. A fourth dielectric layer is formed by filling the trench with a dielectric material, thereby forming a wall fin structure.