The present disclosure provides a semiconductor structure and a manufacturing method thereof, and relates to the technical field of semiconductors. The semiconductor structure includes: a base, including a doped region; a recess, located in the doped region; and a gradient layer, filling the recess, wherein a doping concentration of the gradient layer varies gradually from a bottom of the recess upwards.

A semiconductor device includes a gate structure on a substrate and an epitaxial layer adjacent to the gate structure, in which the epitaxial layer includes a first buffer layer, a second buffer layer on the first buffer layer, a bulk layer on the second buffer layer, a first cap layer on the bulk layer, and a second cap layer on the first cap layer. Preferably, the bottom surface of the first buffer layer includes a linear surface, a bottom surface of the second buffer layer includes a curve, and the second buffer layer includes a linear sidewall.

A semiconductor device and a method of forming the same are provided. The semiconductor device includes a gate stack over an active region and a source/drain region in the active region adjacent the gate stack. The source/drain region includes a first semiconductor layer having a first germanium concentration and a second semiconductor layer over the first semiconductor layer. The second semiconductor layer has a second germanium concentration greater than the first germanium concentration. The source/drain region further includes a third semiconductor layer over the second semiconductor layer and a fourth semiconductor layer over the third semiconductor layer. The third semiconductor layer has a third germanium concentration greater than the second germanium concentration. The fourth semiconductor layer has a fourth germanium concentration less than the third germanium concentration.

A semiconductor device and method of manufacturing the semiconductor device are provided. An exemplary semiconductor device comprises a fin disposed over a substrate, wherein the fin includes a channel region and a source/drain region; a gate structure disposed over the substrate and over the channel region of the fin; a source/drain feature epitaxially grown in the source/drain region of the fin, wherein the source/drain feature includes a top epitaxial layer and a lower epitaxial layer formed below the top epitaxial layer, and the lower epitaxial layer includes a wavy top surface; and a contact having a wavy bottom surface matingly engaged with the wavy top surface of the lower epitaxial layer of the source/drain feature.

A semiconductor device includes a substrate, a device isolation layer on the substrate, the device isolation layer defining a first active pattern, a pair of first source/drain patterns on the first active pattern, the pair of first source/drain patterns being spaced apart from each other in a first direction, and each of the pair of first source/drain patterns having a maximum first width in the first direction, a first channel pattern between the pair of first source/drain patterns, a gate electrode on the first channel pattern and extends in a second direction intersecting the first direction, and a first amorphous region in the first active pattern, the first amorphous region being below at least one of the pair of first source/drain patterns, and having a maximum second width in the first direction that is less than the maximum first width.

An integrated circuit includes a fin active region protruding from a substrate, a plurality of semiconductor patterns on an upper surface of the fin active region, a gate electrode that surrounds the plurality of semiconductor patterns and includes a main gate part on an uppermost one of the plurality of semiconductor patterns and sub gate parts between the plurality of semiconductor patterns, a spacer structure on a sidewall of the main gate part, and a source/drain region at a side of the gate electrode. The source/drain region is connected to the plurality of semiconductor patterns and contacts a bottom surface of the spacer structure. A top portion of the uppermost semiconductor pattern has a first width. A bottom portion of the uppermost semiconductor pattern has a second width smaller than the first width.

Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. A gate structure is arranged over a channel region of a semiconductor body. A first source/drain region is coupled to a first portion of the semiconductor body, and a second source/drain region is located in a second portion the semiconductor body. The first source/drain region includes an epitaxial semiconductor layer containing a first concentration of a dopant. The second source/drain region contains a second concentration of the dopant. The channel region is positioned in the semiconductor body between the first source/drain region and the second source/drain region.

There is provided a semiconductor device having enhanced operation performance by utilizing a cut region where a gate cut is implemented. There is provided a semiconductor device comprising a first active pattern, a second active pattern, a third active pattern, and a fourth active pattern, all of which extend in parallel in a first direction, and are arranged along a second direction intersecting the first direction; a first gate electrode extended in the second direction on the first to fourth active patterns a first cut region extended in the first direction between the first active pattern and the second active pattern to cut the first gate electrode and a second cut region extended in the first direction between the third active pattern and the fourth active pattern to cut the first gate electrode, wherein one or more first dimensional features related to the first cut region is different from one or more second dimensional features related to the second cut region.

A semiconductor device structure is provided. The semiconductor device structure includes a first stacked nanostructure and a second stacked nanostructure formed over a substrate. The semiconductor device structure includes a first gate structure formed over the first stacked nanostructure, and the first gate structure includes a first portion of a gate dielectric layer and a first portion of a filling layer. The semiconductor device structure includes a second gate structure formed over the second stacked nanostructure, and the second gate structure includes a second portion of the gate dielectric layer and a second portion of the filling layer. The semiconductor device structure includes a first isolation layer between the first gate structure and the second gate structure, wherein the first isolation layer has an extending portion which is formed in a recess between the gate dielectric layer and the filling layer.

A memory cell is disclosed. The memory cell includes a first transistor. The first transistor includes a first conduction channel collectively constituted by one or more first nanostructures spaced apart from one another along a vertical direction. The memory cell includes a second transistor electrically coupled to the first transistor in series. The second transistor includes a second conduction channel collectively constituted by one or more second nanostructures spaced apart from one another along the vertical direction. At least one of the one or more first nanostructures is applied with first stress by a first metal structure extending, along the vertical direction, into a first drain/source region of the first transistor.