A semiconductor structure is provided. The semiconductor structure includes an insulator layer, first and second field-effect transistor devices, an isolation field-effect transistor device, front-side gate and back-side gate contacts. Each of the first and second field-effect transistor devices and the isolation field-effect transistor device includes a fin structure and first and second epitaxial source/drain structures. The fin structure includes channel layers and a gate structure that is wrapped around the channel layers. The first and second epitaxial source/drain structures are connected to opposite sides of the channel layers. The isolation field-effect transistor device is kept in the off-state. The front-side gate contact is formed on the first field-effect transistor device and electrically connected to the gate structure of the first field-effect transistor device. The back-side gate contact is formed passing through the insulator layer and electrically connected to the gate structure of the isolation field-effect transistor device.

A semiconductor device includes an active region extending in a first direction; a device isolation layer on side surfaces of the active region and defining the active region; a gate structure intersecting the active region on the active region and extending in a second direction; source/drain regions in regions in which the active region is recessed, on both sides of the gate structure; first protective layers between the device isolation layer and the gate structure; and a buried interconnection line below the source/drain regions and connected to one of the source/drain regions through an upper surface of the buried interconnection line.

Embodiments of the present disclosure includes a method of forming a semiconductor device. The method includes providing a substrate having a plurality of first semiconductor layers and a plurality of second semiconductor layers disposed over the substrate. The method also includes patterning the first semiconductor layers and the second semiconductor layers to form a first fin and a second fin, removing the first semiconductor layers from the first and second fins such that a first portion of the patterned second semiconductor layers becomes first suspended nanostructures in the first fin and that a second portion of the patterned second semiconductor layers becomes second suspended nanostructures in the second fin, and doping a threshold modifying impurity into the first suspended nanostructures in the first fin.

A semiconductor device comprising stacked complimentary transistors are described. In some embodiments, the semiconductor device comprises a first device comprising an enhancement mode III-N heterostructure field effect transistor (HFET), and a second device over the first device. In an example, the second device comprises a depletion mode thin film transistor. In an example, a connector is to couple a first terminal of the first device to a first terminal of the second device.

A vertical nanowire semiconductor device manufactured by a method of manufacturing a vertical nanowire semiconductor device is provided. The vertical nanowire semiconductor device includes a substrate, a first conductive layer in a source or drain area formed above the substrate, a semiconductor nanowire of a channel area vertically upright with respect to the substrate on the first conductive layer, wherein a crystal structure thereof is grown in <111> orientation, a second conductive layer of a drain or source area provided on the top of the semiconductor nanowire, a metal layer on the second conductive layer, a NiSi.sub.2 contact layer between the second conductive layer and the metal layer, a gate surrounding the channel area of the vertical nanowire, and a gate insulating layer located between the channel area and the gate.

The present disclosure relates to a novel integrate-and-fire (IF) neuron circuit using a single-gated feedback field-effect transistor (FBFET) to realize small size and low power consumption. According to the present disclosure, the neuron circuit according to one embodiment may generate potential by charging current input from synapses through a capacitor. In this case, when the generated potential exceeds a threshold value, the neuron circuit may generate and output a spike voltage corresponding to the generated potential using a single-gated feedback field-effect transistor connected to the capacitor. Then, the neuron circuit may reset the generated spike voltage using transistors connected to the feedback field-effect transistor.

Some implementations described herein provide a method. The method includes forming, in a nanostructure transistor device, a recessed portion for a source/drain region of the nanostructure transistor device. The method also includes forming an inner spacer on a bottom of the recessed portion and on sidewalls of the recessed portion. The method further includes etching the inner spacer such that the inner spacer is removed from the bottom and from first portions of the sidewalls, and such that the inner spacer remains on second portions of the sidewalls. The method additionally includes forming, after etching the inner spacer, a buffer layer over a substrate of the nanostructure transistor device at the bottom of the recessed portion. The method further includes forming the source/drain region over the buffer layer in the recessed portion.

The present disclosure describes a method to form a semiconductor device with backside contact structures. The method includes forming a semiconductor device on a first side of a substrate. The semiconductor device includes a source/drain (S/D) region. The method further includes etching a portion of the S/D region on a second side of the substrate to form an opening and forming an epitaxial contact structure on the S/D region in the opening. The second side is opposite to the first side. The epitaxial contact structure includes a first portion in contact with the S/D region in the opening and a second portion on the first portion. A width of the second portion is larger than the first portion.

A method includes etching a semiconductor substrate to form a trench between a first semiconductor strip and a second semiconductor strip. The first semiconductor strip has a first width at about 5 nm below a top of the first semiconductor strip and a second width at about 60 nm below the top of the first semiconductor strip. The first width is smaller than about 5 nm, and the second width is smaller than about 14.5 nm. The trench is filled with dielectric materials to form an isolation region, which is recessed to have a depth. A top portion of the first semiconductor strip protrudes higher than the isolation region to form a protruding fin. The protruding fin has a height smaller than the depth. A gate stack is formed to extend on a sidewall and a top surface of the protruding fin.

The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, first and second contact structures proximate to each other and over the substrate, and first and second dielectric layers formed over the first and second contact structures, respectively. A top portion of the first dielectric layer can include a first dielectric material. A bottom portion of the first dielectric layer can include a second dielectric material different from the first dielectric material. The second dielectric layer can include a third dielectric material different from the first dielectric material.