A MESFET transistor on a horizontal substrate surface with at least one wiring layer on the substrate surface. The transistor comprises source, drain and gate electrodes which are at least partly covered by a semiconducting channel layer. The source, drain and gate electrodes optionally comprise interface contact materials for changing the junction type between each electrode and the channel. The interface between the source electrode and the channel is an ohmic junction, the interface between the drain electrode and the channel is an ohmic junction, and the interface between the gate electrode and the channel is a Schottky junction. The substrate is a CMOS substrate.

A process of forming a nitride semiconductor device is disclosed. The process includes steps of: (a) forming insulating films on a semiconductor stack, where the insulating films include a first silicon nitride (SiN) film, a silicon oxide (SiO.sub.2) film, and a second SiN film; (b) forming an opening in the insulating films; (c) widening the opening in the SiO.sub.2 film; (d) forming a recess in the semiconductor stack using the insulating films as a mask; (e) growing a doped region within the recess and simultaneously depositing the nitride semiconductor material constituting the doped region on the second SiN film; and (f) removing the nitride semiconductor material deposited on the second SiN film and the second SiN film by removing the SiO.sub.2 film.

A logic gate cell structure is disclosed. The logic gate cell structure includes a substrate, a channel layer disposed over the substrate, and a field-effect transistor (FET) contact layer disposed over the channel layer. The FET contact layer is divided by an isolation region into a single contact region and a combined contact region. The channel layer and the FET contact layer form part of a FET device. A collector layer is disposed within the combined contact region over the FET contact layer to provide a current path between the channel layer and the collector layer though the FET contact layer. The collector layer, a base layer, and an emitter layer form part of a bipolar junction transistor.

A method of forming an alignment contact includes: providing a III-nitride substrate; epitaxially growing a first III-nitride layer on the III-nitride substrate, wherein the first III-nitride layer is characterized by a first conductivity type; forming a plurality of III-nitride fins on the first III-nitride layer, wherein each the plurality of III-nitride fins is separated by one of a plurality of first recess regions, wherein the plurality of III-nitride fins are characterized by the first conductivity type; epitaxially regrowing a III-nitride source contact portion on each of the plurality of III-nitride fins; and forming a source contact structure on the III-nitride source contact portions.

In some examples, a transistor comprises a gallium nitride (GaN) layer; a GaN-based alloy layer having a top side and disposed on the GaN layer, wherein source, drain, and gate contact structures are supported by the GaN layer; and a first doped region positioned in a drain access region and extending from the top side into the GaN layer.

An enhancement-mode device includes: a substrate; a channel layer and a barrier layer successively formed on the substrate; an n-type semiconductor layer formed on the barrier layer, a gate region being defined on a surface of the n-type semiconductor layer; a groove that is formed in the gate region and at least partially runs through the n-type semiconductor layer; and a p-type conductor material that is formed on the surface of the n-type semiconductor layer and at least fills the inside of the groove.

A process of forming a field transistor (FET) and a FET are disclosed. The FET includes a nitride semiconductor stack on a substrate. A pair of n.sup.+-regions made of oxide semiconductor material are provided within respective recesses in the semiconductor stack. Protecting layers, each made of oxide material, cover peripheries of the n.sup.+-regions. Electrodes are provided in openings in the protecting layers to be in direct contact with the n.sup.+-regions.

In a first aspect of a present inventive subject matter, a layered structure includes a first semiconductor layer including an -phase crystalline oxide semiconductor with a first composition, and a second semiconductor layer including an -phase crystalline oxide semiconductor with a second composition that is different from the first composition of the first semiconductor layer, and the second semiconductor layer is layered on the first semiconductor layer.

In some examples, a transistor comprises a gallium nitride (GaN) layer; a GaN-based alloy layer having a top side and disposed on the GaN layer, wherein source, drain, and gate contact structures are supported by the GaN layer; and a first doped region positioned in a drain access region and extending from the top side into the GaN layer.

The present disclosure relates to a FET device (10), comprising a substrate (11), a GaN structure (15) covering a portion of the substrate (11), and a gate metal layer (17) on top of the GaN structure (15). The gate metal layer (17) comprises at least one first section (17-1) being formed from a first material composition, and a second section (17-2) being formed from a second material composition that is different from the first material composition, wherein a first interface (41) between the GaN structure (15) and the at least one first section (17-1) of the gate metal layer (17) has ohmic contact properties, and wherein a second interface (43) between the GaN structure (15) and the second section (17-2) of the gate metal layer (17) has non-ohmic contact properties