In an embodiment, a semiconductor device includes an enhancement mode Group III-nitride-based High Electron Mobility Transistor (HEMT) including a drain, a gate, a barrier layer, a channel layer, a barrier layer arranged on the channel layer, and a heterojunction formed between the barrier layer and the channel layer and capable of supporting a two-dimensional electron gas (2DEG). At least one of a thickness and a composition of the barrier layer is configured to decrease a 2DEG density in a channel region compared with a 2DEG density outside of the channel region, wherein the channel region is arranged under the gate and extends a distance d beyond a drain-sided gate edge.

This application provides a high power semiconductor device, which is characterized by forming two diodes connected in parallel and a schottky contact on a channel layer to lower the turn-on voltage and turn-on resistance of the high power semiconductor device at the same time and to enhance the breakdown voltage.

Methods and apparatuses for detecting ammonia are disclosed. A sensor can include a transistor having a gate, a drain, and a source. A layer of ammonia detecting material can be functionally attached to the transistor. The ammonia detecting material can be zinc oxide (ZnO) nanorods, which effectively functionalize the transistor by changing the amount of current that flows through the gate when a voltage is applied. Alternatively, or in addition to ZnO nanorods, films or nanostructure type metal oxides including TiO2, ITO, ZnO, WO.sub.3 and AZO can be used. The transistor is preferably a high electron mobility transistor (HEMT).

A structure having: a plurality of field effect transistors (FETs) connected between a common input and a common output, each one of the field effect transistors comprises: a source region, a drain region, and a gate electrode for controlling carriers through a channel region of a transistor region of the structure between the source region and the drain region; a plurality of diodes, each one of the diodes being associated with a corresponding one of the plurality of FETs, each one of the diodes having an electrode in Schottky contact with a diode region of the corresponding one of the FETs. The gate electrode and the diode electrode extend along parallel lines. The source region, the drain region, the channel region, and a diode region having therein the diode are disposed along a common line.

The present invention realizes a semiconductor device capable of forming a good contact with a 2DEG layer. The semiconductor device includes a recess formed in a partial region of a surface of the barrier layer and having a depth reaching the channel layer, and an electrode formed to cover along the recess. The recess has a first side surface being an exposed surface of the barrier layer and having an angle with respect to a main surface of the substrate, a terrace continuing to the first side surface and being an exposed surface of the channel layer, and a second side surface continuing to the terrace, being an exposed surface of the channel layer, and having an inclination angle smaller than the angle of the first side surface with respect to the main surface of the substrate.

An insulated-gate field effect transistor includes a substrate having a drift region and a source region of first conductivity type, and a base region and shielding region of second conductivity type therein. The base region forms a first P-N junction with the source region and the shielding region extends between the drift region and the base region. A transition region of first conductivity type is provided, which is electrically coupled to the drift region. The transition region extends between a first surface of the substrate and the shielding region, and forms a second P-N junction with the base region. An insulated gate electrode is provided on a first surface of the substrate. The insulated gate electrode has an electrically conductive gate therein with a drain-side sidewall extending intermediate the second P-N junction and an end of the shielding region when viewed in transverse cross-section.

A method for manufacturing a semiconductor device comprises forming a bottom source/drain region on a semiconductor substrate, forming a channel region extending vertically from the bottom source/drain region, growing a top source/drain region from an upper portion of the channel region, and growing a gate region from a lower portion of the channel region under the upper portion, wherein the gate region is on more than one side of the channel region.

A semiconductor device may include a first inverter, a second inverter, a first access transistor, and a second access transistor. A drain electrode of the first access transistor or a source electrode of the first access transistor may be electrically connected to both an output terminal of the first inverter and an input terminal the second inverter. The drain electrode of the first access transistor may be asymmetrical to the source electrode of the first access transistor with reference to a gate electrode of the first access transistor. A drain electrode of the second access transistor or a source electrode of the second access transistor may be electrically connected to both an output terminal of the second inverter and an input terminal the first inverter.

A semiconductor device includes a substrate, a first semiconductor layer formed over the substrate, a second semiconductor layer formed over the first semiconductor layer, a third semiconductor layer formed over the second semiconductor layer, and a gate electrode, a source electrode, and a drain electrode that are formed over the third semiconductor layer. The first semiconductor layer includes a first nitride semiconductor. The second semiconductor includes a second nitride semiconductor. The third semiconductor layer includes a third nitride semiconductor. The concentration of oxygen included in the second semiconductor layer is less than 5.010.sup.18 cm.sup.3. The concentration of oxygen included in the third semiconductor layer is greater than or equal to 5.010.sup.18 cm.sup.3.

Semiconductor devices including an elevated or raised doped crystalline structure extending from a device layer are described. In embodiments, III-N transistors include raised crystalline n+ doped source/drain structures on either side of a gate stack. In embodiments, an amorphous material is employed to limit growth of polycrystalline source/drain material, allowing a high quality source/drain doped crystal to grow from an undamaged region and laterally expand to form a low resistance interface with a two-degree electron gas (2DEG) formed within the device layer. In some embodiments, regions of damaged GaN that may spawn competitive polycrystalline overgrowths are covered with the amorphous material prior to commencing raised source/drain growth.