A lateral transistor tile is formed with first and second collector regions that longitudinally span first and second sides of the transistor tile; and a base region and an emitter region that are between the first and second collector regions and are both centered on a longitudinal midline of the transistor tile. A base-collector current, a collector-emitter current, and a base-emitter current flow horizontally; and the direction of the base-emitter current is perpendicular to the direction of the base-collector current and the collector-emitter current. Lateral BJT transistors having a variety of layouts are formed from a plurality of the tiles and share common components thereof.

In some embodiments, a bipolar junction transistor (BJT) is provided. The BJT may include a collector region that is disposed within a semiconductor substrate. A base region that is disposed within the semiconductor substrate and arranged within the collector region. An emitter region that is disposed within the semiconductor substrate and arranged within the base region. A pre-metal dielectric layer that is disposed over an upper surface of the semiconductor substrate and that separates the upper surface of the semiconductor substrate from a lowermost metal interconnect layer. A first plurality of dishing prevention columns that are arranged over the emitter region and within the pre-metal dielectric layer, where the plurality of dishing prevention columns each include a dummy gate that is conductive and electrically floating.

In some embodiments, a bipolar junction transistor (BJT) is provided. The BJT may include a collector region that is disposed within a semiconductor substrate. A base region that is disposed within the semiconductor substrate and arranged within the collector region. An emitter region that is disposed within the semiconductor substrate and arranged within the base region. A pre-metal dielectric layer that is disposed over an upper surface of the semiconductor substrate and that separates the upper surface of the semiconductor substrate from a lowermost metal interconnect layer. A first plurality of dishing prevention columns that are arranged over the emitter region and within the pre-metal dielectric layer, where the plurality of dishing prevention columns each include a dummy gate that is conductive and electrically floating.

Semiconductor structures of bipolar junction transistor (BJT) are provided. A first active region of a collection region is formed over a first P-type well region. Second and third active regions of a base region are formed over an N-type well region. A fourth active region of an emitter region is formed over a second P-type well region. The first active region includes a plurality of first fins and a plurality of first source/drain features epitaxially grown on the first fins. Each of the second and third active regions includes a plurality of second fins and a plurality of second source/drain features epitaxially grown on the second fins. The fourth active region includes a plurality of third fins and a plurality of third source/drain features epitaxially grown on the third fins. The second and third active regions are disposed on opposite sides of the fourth active region.

High-performance lateral bipolar junction transistors (BJTs) are provided in which a lightly doped upper intrinsic base region is formed between a lower intrinsic base region and an extrinsic base region. The lightly doped upper intrinsic base region provides two electron paths which contribute to the collector current, I.sub.C. The presence of the lightly doped upper intrinsic base region increases the total I.sub.C and leads to higher current gain, , if there is no increase of the base current, I.sub.B.

High-performance lateral bipolar junction transistors (BJTs) are provided in which a lightly doped upper intrinsic base region is formed between a lower intrinsic base region and an extrinsic base region. The lightly doped upper intrinsic base region provides two electron paths which contribute to the collector current, I.sub.C. The presence of the lightly doped upper intrinsic base region increases the total I.sub.C and leads to higher current gain, , if there is no increase of the base current, I.sub.B.

A semiconductor device including a base region present within a fin semiconductor structure that is present atop a dielectric substrate. An epitaxial emitter region and epitaxial collector region are present on opposing sides and in direct contact with the fin semiconductor structure. An epitaxial extrinsic base region is present on a surface of the fin semiconductor substrate that is opposite the surface of the fin semiconductor structure that is in contact with the dielectric base.

A structure and method of forming a lateral bipolar junction transistor (LBJT) that includes: a first base layer, a second base layer over the first base layer, and an emitter region and collector region present on opposing sides of the first base layer, where the first base layer has a wider-band gap than the second base layer, and where the first base layer includes a III-V semiconductor material.

BJT devices with 3D wrap around emitter are provided. In one aspect, a method of forming a BJT device includes: forming a substrate including a first doped layer having a dopant concentration of from about 110.sup.20 at. % to about 510.sup.20 at. % and ranges therebetween, and a second doped layer having a dopant concentration of from about 110.sup.15 at. % to about 110.sup.18 at. % and ranges therebetween, wherein the first and second doped layers form a collector; patterning a fin(s) in the substrate; forming bottom spacers at a bottom of the fin(s); forming a base(s) that wraps around the fin(s); forming an emitter(s) that wraps around the base(s); and forming sidewall spacers alongside the emitter(s). A BJT device is also provided.

A lateral bipolar junction transistor (LBJT) device that may include a dielectric stack including a pedestal of a base region passivating dielectric and a nucleation dielectric layer; and a base region composed of a germanium containing material or a type III-V semiconductor material in contact with the pedestal of the base region passivating dielectric. An emitter region and collector region may be present on opposing sides of the base region contacting a sidewall of the pedestal of the base region passivating dielectric and an upper surface of the nucleation dielectric layer.