An ESD protection device including a PNP transistor connected to an input pad, a diode connected to the PNP transistor and connected to an output pad, and an NMOS transistor connected to the PNP transistor and the output pad, wherein the diode, PNP transistor, and NMOS transistor are configured to route different levels of an electrostatic discharge (ESD) current pulse from the input pad to the output pad.

The present disclosure relates to semiconductor structures and, more particularly, to bipolar transistors and methods of manufacture. The structure includes: an emitter in a semiconductor substrate; a collector in the semiconductor substrate; a base contact region in the semiconductor substrate and adjacent to the collector and the emitter; and a shallow trench isolation structure overlapping the base contact region and separating the base contact region from the emitter and the collector.

Embodiments of the disclosure provide a lateral bipolar transistor on a semiconductor fin and methods to form the same. A bipolar transistor structure according to the disclosure may include a doped semiconductor layer coupled to a base contact. A first semiconductor fin on the doped semiconductor layer may have a first doping type. An emitter/collector (E/C) material may be on a sidewall of an upper portion of the first semiconductor fin. The E/C material has a second doping type opposite the first doping type. The E/C material is coupled to an E/C contact.

Bipolar junction transistor structures and methods for making the same are provide. The method includes: providing a substrate with an insulator layer and a device layer over the insulator layer, forming an intrinsic base from the device layer, forming emitter and collector regions from the device layer, and after forming i) the intrinsic base and ii) the emitter and collector regions, depositing a single crystalline extrinsic base over the intrinsic base.

A HVJT structure of HVIC includes P-type substrate. Epitaxial layer is formed on the substrate. N-type doped structure is formed in the epitaxial layer, contacting with the substrate. P-type doped structure is in the N-type doped structure connecting with anode. The substrate, the N-type doped structure and the P-type doped structure form a PNP path along a perpendicular direction to the substrate, wherein NP provide bootstrap diode function and surround the high-side circuit at a horizontal direction. N-type cathode structure is in the epitaxial layer. N-type epitaxial doped region contacts with the substrate, between the PNP path and the N-type cathode structure, also surrounding the high-side circuit. Gate structure is over the N-type epitaxial doped region, between the P-type doped structure and N-type cathode structure. P-type base doped structure is in the epitaxial layer adjacent to the N-type doped structure, to provide a substrate voltage to the substrate.

A method for manufacturing a fin-type bipolar semiconductor device includes providing a substrate comprising a first region of a first conductivity type and a second region of a second conductivity type adjacent the first region, etching the substrate to form a third region in the first region, a first set of fins on the third region, a fourth region in the second region, and a second set of fins on the fourth region, performing a first implantation into a first portion of the second set of fins and a corresponding portion of the fourth region to form an emitter region of the first conductivity type, a remaining portion of the fourth region not being doped forming a base region adjacent the emitter region and forming a junction in the fourth region, and performing a second implantation into a second portion of the second set of fins different from the first portion.

In some embodiments, a bipolar junction transistor (BJT) is provided. The BJT may include a collector region that is disposed within a semiconductor substrate. A base region that is disposed within the semiconductor substrate and arranged within the collector region. An emitter region that is disposed within the semiconductor substrate and arranged within the base region. A pre-metal dielectric layer that is disposed over an upper surface of the semiconductor substrate and that separates the upper surface of the semiconductor substrate from a lowermost metal interconnect layer. A first plurality of dishing prevention columns that are arranged over the emitter region and within the pre-metal dielectric layer, where the plurality of dishing prevention columns each include a dummy gate that is conductive and electrically floating.

In some embodiments, a bipolar junction transistor (BJT) is provided. The BJT may include a collector region that is disposed within a semiconductor substrate. A base region that is disposed within the semiconductor substrate and arranged within the collector region. An emitter region that is disposed within the semiconductor substrate and arranged within the base region. A pre-metal dielectric layer that is disposed over an upper surface of the semiconductor substrate and that separates the upper surface of the semiconductor substrate from a lowermost metal interconnect layer. A first plurality of dishing prevention columns that are arranged over the emitter region and within the pre-metal dielectric layer, where the plurality of dishing prevention columns each include a dummy gate that is conductive and electrically floating.

A bipolar junction transistor (BJT) includes an emitter region, abase region on one side of the emitter region, and a collector region on the other side of the base region. The emitter region includes first fins extending along a first direction, a first metal gate extending across the first fins along a second direction, a second metal gate in parallel with the first metal gate, and an emitter contact plug on the first fins between the first metal gate and the second metal gate. The base region includes second fins extending along the first direction, the first metal gate and the second metal gate extending across the second fins along the second direction, and a base contact plug on the second fins between the first metal gate and the second metal gate. The emitter contact plug is aligned with the base contact plug.

Embodiments of the disclosure provide a lateral bipolar transistor structure with inner and outer spacers, and related methods. A lateral bipolar transistor structure may have an emitter/collector (E/C) layer over an insulator. The E/C layer has a first doping type. A first base layer is on the insulator and adjacent the E/C layer. The first base layer has a second doping type opposite the first doping type. A second base layer is on the first base layer and having the second doping type. A dopant concentration of the second base layer is greater than a dopant concentration of the first base layer. An inner spacer is on the E/C layer and adjacent the second base layer. An outer spacer is on the E/C layer and adjacent the inner spacer.