A semiconductor device including a Horizontal Current Bipolar Transistor (HCBT) and methods of manufacture. The device has a semiconductor substrate of a first conductivity type defining a wafer plane parallel to the semiconductor substrate and has a base region and a collector region forming a first metallurgical junction. The device also has an emitter region forming a second metallurgical junction with the base region. A flat portion of the first metallurgical junction and a flat portion of the second metallurgical junction are substantially parallel to each other and close an acute angle with the wafer plane. At least a portion of the base region comprises silicon-germanium alloy or silicon-germanium-carbon alloy.

Structures for a bipolar junction transistor and methods of forming a structure for a bipolar junction transistor. The structure includes a collector having a raised portion, an emitter having a raised portion, and a base laterally arranged between the raised portion of the emitter and the raised portion of the collector. The base includes an intrinsic base layer and an extrinsic base layer stacked with the intrinsic base layer. The structure further includes a stress liner positioned to overlap with the raised portion of the collector, the raised portion of the emitter, and the extrinsic base layer.

A method for producing a semiconductor device, the method includes, forming, on a substrate made from a semiconductor substance, at least one bipolar junction (BJ) transistor including a first terminal connected to a first well, the first well formed in the substrate and includes a first dopant having a first dopant concentration. At least one non-BJ transistor is formed on the substrate, the non-BJ transistor includes a second terminal connected to a second well, and the second well formed in the substrate and includes a second dopant having a same polarity as the first dopant. The first dopant concentration of the BJ transistor is higher than the second dopant concentration of the non-BJ transistor.

Structures including III-V compound semiconductor-based devices and silicon-based devices integrated on a semiconductor substrate and methods of forming such structures. The structure includes a substrate having a device layer, a handle substrate, and a buried insulator layer between the handle substrate and the device layer. The structure includes a first semiconductor layer on the device layer in a first device region, and a second semiconductor layer on the device layer in a second device region. The first semiconductor layer contains a III-V compound semiconductor material, and the second semiconductor layer contains silicon. A first device structure includes a gate structure on the first semiconductor layer, and a second device structure includes a doped region in the second semiconductor layer. The doped region and the second semiconductor layer define a p-n junction.

The disclosure provides a lateral bipolar transistor structure with a base layer over a semiconductor buffer, and related methods. A lateral bipolar transistor structure may include an emitter/collector (E/C) layer over an insulator. The E/C layer has a first doping type. A semiconductor buffer is adjacent the insulator. A base layer is on the semiconductor buffer and adjacent the E/C layer, the base layer including a lower surface below the E/C layer and an upper surface above the E/C layer. The base layer has a second doping type opposite the first doping type.

A method of subdividing a semiconductor wafer is described with trenches in order to provide separate, electrically isolated regions that can be used to hold components that operate at different voltages. There is also described a masking and etching process of forming collector and emitter regions of a lateral bipolar transistor, from a layer of polysilicon deposited on a patterned later of silicon dioxide.

The present disclosure relates to semiconductor structures and, more particularly, to electrostatic discharge (ESD) devices and methods of manufacture. The structure includes a bipolar transistor device, including a base region, having a base contact region, in a first well of a first conductivity type, a collector region, having a collector contact region, in a second well of a second conductivity type, and an emitter region, having an emitter contact region, in the first well, located between the base contact region and the second well, and a reverse-doped resistance well, of the second conductivity type, located in the first well of the first conductivity type between the base contact region and the emitter contact region structured to decrease turn-on voltage of the bipolar transistor device.

Disclosed semiconductor structure embodiments include a bipolar junction device configured to have a high holding voltage. The device includes base, collector and emitter terminals. The high holding voltage is achieved because of a uniquely configured emitter terminal. Specifically, the device includes a base well region, which has a first-type conductivity. The emitter terminal includes, adjacent to the base well region (e.g., within and/or on the base well region), an emitter contact region, which has a second-type conductivity, and an ancillary emitter region, which abuts the emitter contact region and which has the first-type conductivity at a higher conductivity level than the base well region. Embodiments vary with regard to the shapes of the emitter contact region and ancillary emitter region. Embodiments also vary with regard to the structures used to isolate the collector terminal from the emitter terminal and with regard to the areas covered by silicide layers.

A bipolar transistor is capable of reducing variations in electrical characteristics. A bipolar transistor 100 includes: a collector region 150 which is a predetermined region in a P-type semiconductor substrate 110; a base region 140 which is formed within the collector region 150 and is an N-type well region; a polysilicon 130 formed on the base region 140 via an insulating film 131 and having an outer periphery, as viewed in a plan view, in a rectangular ring shape; and a P-type emitter region 120 surrounded by the polysilicon 130 and formed within the base region 140. The polysilicon 130 includes an extension portion 130a extending inside a contact region 141 of the base region 140 and electrically connected to the base region 140.

The present disclosure relates to semiconductor structures and, more particularly, to a bipolar transistor with thermal conductor and methods of manufacture. The structure includes: a base formed within a semiconductor substrate; a thermal conductive material under the base and extending to an underlying semiconductor material; an emitter on a first side of the base; and a collector on a second side of the base.