Embodiments are directed to two-dimensional electron gas (2DEG)-confined 2DEG devices and methods. One such device includes a substrate and a heterostructure on the substrate. The heterostructure includes a first semiconductor layer, a second semiconductor layer, and a 2DEG layer between the first and second semiconductor layers. The device further includes a 2DEG device having a conduction channel in the 2DEG layer. An isolation electrode overlies the heterostructure and at least partially surrounds a periphery of the 2DEG device. The isolation electrode, in use, interrupts the 2DEG layer in response to an applied voltage.

In some embodiments, the present disclosure relates to an integrated transistor device, including a first barrier layer arranged over a substrate. Further, an undoped layer may be arranged over the first barrier layer and have a n-channel device region laterally next to a p-channel device region. The n-channel device region of the undoped layer has a topmost surface that is above a topmost surface of the p-channel device region of the undoped layer. The integrated transistor device may further comprise a second barrier layer over the n-channel device region of the undoped layer. A first gate electrode is arranged over the second barrier layer, and a second gate electrode is arranged over the p-channel device region of the undoped layer.

A process of forming a field transistor (FET) and a FET are disclosed. The FET includes a nitride semiconductor stack on a substrate. A pair of n.sup.+-regions made of oxide semiconductor material are provided within respective recesses in the semiconductor stack. Protecting layers, each made of oxide material, cover peripheries of the n.sup.+-regions. Electrodes are provided in openings in the protecting layers to be in direct contact with the n.sup.+-regions.

A semiconductor device includes a semiconductor substrate configured to include a channel, first and second ohmic contacts supported by the semiconductor substrate, in ohmic contact with a contact region formed within the semiconductor substrate, and spaced from one another for current flow between the first and second ohmic contacts through the channel, and first and second dielectric layers supported by the semiconductor substrate. At least one of the first and second ohmic contacts extends through respective openings in the first and second dielectric layers. The second dielectric layer is disposed between the first dielectric layer and a surface of the semiconductor substrate, and the second dielectric layer includes a wet etchable material having an etch selectivity to a dry etchant of the first dielectric layer.

A semiconductor structure that occupies only one areal device area is provided that includes a charge storage region sandwiched between a pFET nanosheet device and an nFET nanosheet device. The charge storage region is an epitaxial oxide nanosheet that is lattice matched to an underlying first silicon channel material nanosheet and an overlying second silicon channel material nanosheet. The semiconductor structure can be used as an EPROM device.

In some examples, a transistor comprises a gallium nitride (GaN) layer; a GaN-based alloy layer having a top side and disposed on the GaN layer, wherein source, drain, and gate contact structures are supported by the GaN layer; and a first doped region positioned in a drain access region and extending from the top side into the GaN layer.

The present disclosure relates to semiconductor power devices, and in particular, to a high-electron-mobility transistor (HEMT) with high voltage endurance capability and a preparation method thereof. The high-electron-mobility transistor with high voltage endurance capability includes a gate electrode, a source electrode, a drain electrode, a barrier layer, a P-type nitride semiconductor layer and a substrate, wherein the P-type nitride semiconductor layer is between the barrier layer and the substrate, which is insufficient to significantly deplete a two-dimensional electron gas in a channel except a gate stack, the source electrode is in electrical contact with the P-type nitride semiconductor layer, and the source electrode and the drain electrode are both in electrical contact with the two-dimensional electron gas.

The present disclosure provide a semiconductor device, a method for manufacturing a semiconductor device and an electronic apparatus. The device includes: a substrate; a first semiconductor layer formed on the substrate; a second semiconductor layer formed on the first semiconductor layer, the first semiconductor layer having a smaller band gap than the second semiconductor layer; a first electrode and a third electrode formed on the first or second semiconductor layer; a second electrode formed on the second semiconductor layer, and a third semiconductor layer.

The present disclosure provides a semiconductor device and a method of fabricating the same. The device comprises a substrate; a first semiconductor layer formed on the substrate; a second semiconductor layer formed on the first semiconductor layer; the first semiconductor layer having a smaller forbidden band width than the second semiconductor layer; and a first electrode, a second electrode, and a third electrode formed on the second semiconductor layer; the first semiconductor layer corresponding to the third electrode has a strongly P-type doped first region, and the first semiconductor layer corresponding to the second electrode has a weakly P-type doped second region. The present disclosure contributes to achievement of one of the effects of: reducing a gate leakage current, having a high threshold voltage, high power, and high reliability, allowing a low on-resistance and a normally-off state of the device, and providing a stable threshold voltage, so that the semiconductor device has good switching characteristics.

A circuit structure including a first gate structure, a first multi-connected channel layer and a second transistor is provided. The first gate structure has a first extension direction, and the first gate structure has a first end and a second end opposite to each other. The first gate structure is fully surrounded by the first multi-connected channel layer, and a plane direction of the multi-connected channel layer is perpendicular to the first extension direction. The first gate structure and the first multi-connected channel layer form a first transistor. The second transistor is disposed in the first multi-connected channel layer. A second gate structure or a channel of the second transistor is electrical connected to the first multi-connected channel layer.