A semiconductor device including an active pattern on a substrate and extending lengthwise in a first direction parallel to an upper surface of the substrate; a gate structure on the active pattern, the gate structure extending in a second direction parallel to the upper surface of the substrate and crossing the first direction; channels spaced apart from each other along a third direction perpendicular to the upper surface of the substrate, each of the channels extending through the gate structure along the first direction; a source/drain layer on a portion of the active pattern adjacent to the gate structure in the first direction, the source/drain layer contacting the channels; inner spacers between the gate structure and the source/drain layer, the inner spacers contacting the source/drain layer; and channel connection portions between each of the inner spacers and the gate structure, the channel connection portions connecting the channels with each other.

A method for fabricating a semiconductor device including vertical transistors having uniform channel length includes defining a channel length of at least one first fin formed on a substrate in a first device region and a channel length of at least one second fin formed on the substrate in a second device region. Defining the channel lengths includes creating at least one divot in the second device region. The method further includes modifying the channel length of the at least one second fin to be substantially similar to the channel length of the at least one first fin by filling the at least one divot with additional gate conductor material.

Presented is a lateral fin static induction transistor including a semi conductive substrate, source and drain regions extending from an optional buffer layer of same or varied thickness supported by the semi conductive substrate, a semi conductive channel electrically coupling the source region to the drain region of the transistor, a portion of the semi conductive channel being a fin and having a face covered by a gated structure, thereby defining a gated channel within the semi conductive channel, the semi conductive channel further including a drift region electrically coupling the gated channel to the drain region of the transistor.

A circuit structure including a first gate structure, a first multi-connected channel layer and a second transistor is provided. The first gate structure has a first extension direction, and the first gate structure has a first end and a second end opposite to each other. The first gate structure is fully surrounded by the first multi-connected channel layer, and a plane direction of the multi-connected channel layer is perpendicular to the first extension direction. The first gate structure and the first multi-connected channel layer form a first transistor. The second transistor is disposed in the first multi-connected channel layer. A second gate structure or a channel of the second transistor is electrical connected to the first multi-connected channel layer.

A HEMT comprising: a substrate; a channel layer coupled to the substrate; a source electrode coupled to the channel layer; a drain electrode coupled to the channel layer; and a gate electrode coupled to the channel layer between the source electrode and the drain electrode; wherein the channel layer comprises: at least a first GaN layer; and a first graded AlGaN layer on the first GaN layer, the Al proportion of the first graded AlGaN layer increasing with the distance from the first GaN layer.

Presented is a lateral fin static induction transistor including a semi conductive substrate, source and drain regions extending from an optional buffer layer of same or varied thickness supported by the semi conductive substrate, a semi conductive channel electrically coupling the source region to the drain region of the transistor, a portion of the semi conductive channel being a fin and having a face covered by a gated structure, thereby defining a gated channel within the semi conductive channel, the semi conductive channel further including a drift region electrically coupling the gated channel to the drain region of the transistor.

A sensing device includes a first III-V compound stack and a second III-V compound stack. The first III-V compound stack has a first sensing area, and the second III-V compound stack has a second sensing area. A passivation layer fully covers the second sensing area. The first III-V compound stack is physically separated from the second III-V compound stack, and has material compositions and structures same as the second III-V compound stack.

A high electron mobility transistor (HEMT) includes a silicon substrate, an unintentionally doped gallium nitride (UID GaN) layer over the silicon substrate. The HEMT further includes a donor-supply layer over the UID GaN layer, a gate structure, a drain, and a source over the donor-supply layer. The HEMT further includes a dielectric layer having one or more dielectric plug portions in the donor-supply layer and top portions between the gate structure and the drain over the donor-supply layer. A method for making the HEMT is also provided.

A high electron mobility transistor (HEMT) made of primarily nitride semiconductor materials is disclosed. The HEMT, which is a type of reverse HEMT, includes, on a C-polar surface of a SiC substrate, a barrier layer and a channel layer each having N-polar surfaces in respective top surfaces thereof. The HEMT further includes an intermediate layer highly doped with impurities and a Schottky barrier layer on the channel layer. The Schottky barrier layer and a portion of the intermediate layer are removed in portions beneath non-rectifying electrodes but a gate electrode is provided on the Schottky barrier layer.

A method of manufacturing a semiconductor device is provided. The method includes forming a channel layer and an active layer over a substrate; forming a doped epitaxial layer over the active layer; patterning the doped epitaxial layer, the active layer, and the channel layer to form a fin structure comprising a doped epitaxial fin portion, an active fin portion below the doped epitaxial fin portion, and a channel fin portion below the active fin portion; removing the doped epitaxial fin portion; and forming a gate electrode at least partially extending along a sidewall of the fin structure to form a Schottky barrier between the gate electrode and the fin structure after removing the doped epitaxial fin portion.