Provided is a compound semiconductor device. The compound semiconductor device according to embodiments of the inventive concept includes a first semiconductor layer having a fin extending in a first direction on a substrate, an upper gate electrode extending in a second direction perpendicular to the first direction on the first semiconductor layer, a second semiconductor layer disposed between a sidewall of the fin and the upper gate electrode, a dielectric layer disposed between a top surface of the fin and the upper gate electrode, and a lower gate structure connected to a bottom surface of the first semiconductor layer by passing through the substrate.

A semiconductor device includes source and drain regions, a channel region between the source and drain regions, and a gate structure over the channel region. The gate structure includes a gate dielectric over the channel region, a work function metal layer over the gate dielectric and comprising iodine, and a fill metal over the work function metal layer.

A semiconductor device (having a CMOS architecture) includes first to fourth cell regions Each of the first and second cell regions includes a pair of first and second stacks of nanosheets relative to, e.g., the Z-axis. The nanosheets of the first stack have a first dopant-type, e.g., N-type. The nanosheets of the second stack have a second dopant type, e.g., P-type. Each pair of first and second stacks represents a CMOS architecture relative to a second direction, e.g., the Y-axis Each of the third and fourth cell regions has CFET architecture, the CFET architecture being a type of CMOS architecture relative to the Z-axis. The third and fourth cell regions are adjacent each other relative to the Y-axis. The first and second active regions are on corresponding first and second sides of each of the third and fourth active regions. The first and second cell regions are non-CFET cell regions.

A high current density, low contact resistance contact for wide bandgap (WBG) or ultra-wide bandgap materials (UWBG) is disclosed. The contact is lithographically formed so that a total perimeter length of the contact structure is at least twice the length of the side of a contact pad closest to the gate in a high electron mobility transistor (HEMT). The contact structure may take the form of a plurality of columns having various cross-sectional shapes, or may take the form of a convoluted geometrical shape, such as a comb-like, serpentine, or spiral shape. The depth of the contact structure permits direct contact with the two-dimensional electron gas (2DEG) in the HEMT by the perimeter of the contact structure. The contact structure is formed of at least one metal layer, at least one doped material regrown layer, or at least one implanted region. The contact structure may be applied to other WBG and UWBG devices.

A method of fabricating a semiconductor device includes providing a substrate having a layered fin structure thereon. The layered fin structure includes base fin portion, a sacrificial portion provided on the base fin portion and a channel portion provided on the sacrificial portion. A doping source film is provided on the substrate over the layered fin structure, and diffusing doping materials from the doping source film into a portion of the layered fin structure other than the channel portion to form a diffusion doped region in the layered fin structure. An isolation material is provided on the substrate over at least the diffusion doped region of the layered fin structure.

There is provided a nitride semiconductor epitaxial substrate, including: a substrate; a first nitride semiconductor layer formed on the substrate, as an electron transit layer in which two-dimensional electron gas exists; and a second nitride semiconductor layer formed on the first nitride semiconductor layer, as an electron supply layer, wherein the second nitride semiconductor layer includes a portion in which a hydrogen concentration is higher than that of the first nitride semiconductor layer and a difference of the hydrogen concentration from that of the first nitride semiconductor layer is 210.sup.18 cm.sup.3 or less.

A novel design for a nitrogen polar high-electron-mobility transistor (HEMT) structure comprising a GaN/InGaN composite channel. As A novel design for a nitrogen polar high-electron-mobility transistor (HEMT) structure comprising a GaN/InGaN composite channel. As illustrated herein, a thin InGaN layer introduced in the channel increases the carrier density, reduces the electric field in the channel, and increases the carrier mobility. The dependence of p on InGaN thickness (.sup.tInGaN) and indium composition (.sup.xIn) was investigated for different channel thicknesses. With optimized .sup.tInGaN and .sup.xIn, significant improvements in electron mobility were observed. For a 6 nm channel HEMT, the electron mobility increased from 606 to 1141 cm.sup.2/(V.Math.s) when the 6 nm thick pure GaN channel was replaced by the 4 nm GaN/2 nm In.sub.0.1Ga.sub.0.9N composite channel.

A method for manufacturing a semiconductor device includes forming a plurality of silicon germanium and silicon layers on a semiconductor substrate in a stacked configuration comprising a repeating arrangement of a silicon layer stacked on a silicon germanium layer. The stacked configuration is patterned into a plurality of patterned stacks spaced apart from each other. The patterning forms a plurality of recessed portions in the substrate. In the method, the silicon germanium layers are etched to remove portions of the silicon germanium layers from exposed lateral sides of the silicon germanium layers, and inner spacer layers are formed in place of the removed portions. A plurality of lower epitaxial layers are grown in the recessed portions. A plurality of epitaxial source/drain regions are grown from the lower epitaxial layers and from exposed lateral sides of the silicon layers.

Device architectures based on trapping and de-trapping holes or electrons and/or recombination of both types of carriers are obtained by carrier trapping either in near-interface deep ambipolar states or in quantum wells/dots, either serving as ambipolar traps in semiconductor layers or in gate dielectric/barrier layers. In either case, the potential barrier for trapping is small and retention is provided by carrier confinement in the deep trap states and/or quantum wells/dots. The device architectures are usable as three terminal or two terminal devices.

A semiconductor device and a method for manufacturing the same are provided in this disclosure. The semiconductor device includes a semiconductor heterostructure layer. The semiconductor heterostructure layer includes alternating first semiconductor material layers and second semiconductor material layers. Two-dimensional electron gas (2DEG) may be generated between each first semiconductor material layer and adjacent second semiconductor material layer. A conductive structure, including a plurality of conductive fingers extends from a surface of the semiconductor heterostructure layer into the semiconductor heterostructure layer. The plurality of conductive fingers are arranged in a direction substantially parallel to the surface. The lengths of the plurality of conductive fingers progressively increase in that direction so that an end portion of each conductive finger is respectively positioned in a different second semiconductor material layer and is not in contact with the 2DEG.