A semiconductor device includes source and drain regions, a channel region between the source and drain regions, and a gate structure over the channel region. The gate structure includes a gate dielectric over the channel region, a work function metal layer over the gate dielectric and comprising iodine, and a fill metal over the work function metal layer.

A semiconductor device formed by forming a stack of alternating horizontal nanosheet layers, recessing the stack for an n-type field effect transistor (nFET), growing crystalline semiconductor adjacent to the stack, forming vertical nanosheets from the crystalline semiconductor, forming inner spacers between the vertical nanosheets, and forming a high-k metal gate structure around the horizontal nanosheets and the vertical nanosheets.

A semiconductor device includes a barrier region and a channel region, source and drain electrodes, and a gate structure that is configured to control a conductive connection between the source and drain electrodes, wherein the barrier region comprises a first barrier layer and a second barrier layer, wherein in a central portion of the device the second barrier layer is the only layer that is disposed over the channel region, wherein in outer lateral portions of the device the first barrier layer is disposed over the channel region, wherein the first and second barrier layers are each III-V semiconductor alloys, and wherein a molar fraction of a second type III element in the central portion is higher than a molar fraction of the second type III element in the first barrier layer.

The present disclosure provides a semiconductor device and a manufacturing method thereof. The semiconductor device comprises a substrate, a groove formed on the substrate, a channel layer structure grown under restriction of the groove structure, the channel layer structure being exposed from an upper surface of the substrate; a barrier layer covering the exposed channel layer structure, a two-dimensional electron gas and a two-dimensional hole gas respectively formed on a second face and a first face of the channel layer structure, and a source, a gate, and a drain formed on the first face/second face of the channel layer structure, and a bottom electrode formed on the second face/first face of the channel layer structure. The semiconductor device can reduce the gate leakage current, has a high threshold voltage, high power, and high reliability, can achieve a low on-resistance and a normally off state of the device, and can provide a stable threshold voltage, such that the semiconductor device has good switching characteristics. Moreover, the local electric field intensity may be effectively reduced, and the overall performance and reliability of the device may be improved; and the structure and manufacturing process of the semiconductor device are relatively simple, which can effectively reduce the manufacturing cost.

The present disclosure provide a semiconductor device, a method for manufacturing a semiconductor device and an electronic apparatus. The device includes: a substrate; a first semiconductor layer formed on the substrate; a second semiconductor layer formed on the first semiconductor layer, the first semiconductor layer having a smaller band gap than the second semiconductor layer; a first electrode and a third electrode formed on the first or second semiconductor layer; a second electrode formed on the second semiconductor layer, and a third semiconductor layer.

A high-electron mobility transistor includes a substrate layer, a first buffer layer provided on the substrate layer, a barrier layer provided on the first buffer layer, a source provided on the barrier layer, a drain provided on the barrier layer, and a gate provided on the barrier layer. The transistor further includes a p-type material layer having a length parallel to a surface of the substrate layer over which the first buffer layer is provided, the length of the p-type material layer being less than an entire length of the substrate layer. The p-type material layer is provided in one of the following: the substrate layer, or the first buffer layer. A process of making the high-electron mobility transistor is disclosed as well.

Methods of manufacturing device assemblies, as well as associated semiconductor assemblies, devices, systems are disclosed herein. In one embodiment, a method of forming a semiconductor device assembly includes forming a semiconductor device assembly that includes a handle substrate, a semiconductor structure having a first side and a second side opposite the first side, and an intermediary material between the semiconductor structure and the handle substrate. The method also includes removing material from the semiconductor structure to form an opening extending from the first side of the semiconductor structure to at least the intermediary material at the second side of the semiconductor structure. The method further includes removing at least a portion of the intermediary material through the opening in the semiconductor structure to undercut the second side of the semiconductor structure.

A cluster of non-collapsed nanowires, a template to produce the same, methods to obtain the template and to obtain the cluster by using the template, and devices having the cluster. The cluster and the template both have an interconnected region and an interconnection-free region.

The tunneling channel of a field effect transistor comprising a plurality of tunneling elements contacting a channel substrate. Applying a source-drain voltage of greater than a turn-on voltage produces a source-drain current of greater than about 10 pA. Applying a source-drain voltage of less than a turn-on voltage produces a source-drain current of less than about 10 pA. The turn-on voltage at room temperature is between about 0.1V and about 40V.

III-nitride materials are generally described herein, including material structures comprising III-nitride material regions and silicon-containing substrates. Certain embodiments are related to gallium nitride materials and material structures comprising gallium nitride material regions and silicon-containing substrates.