A High Electron Mobility Transistor (HEMT) and a process of forming the same are disclosed. The HEMT includes a substrate, a channel layer, a barrier layer, and heavily doped regions made of metal oxide. The channel layer and the barrier layer provide recesses and a mesa therebetween. The heavily doped regions are formed by partially removing in a portion thereof on the mesa and have slant surfaces facing the gate electrode. The slant surfaces make angle of 135° to 160° against the top horizontal level of the mesa.

Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment, a semiconductor device comprises a stack of semiconductor channels with a first end and second end. In an embodiment, individual ones of the semiconductor channels comprise a nitrided surface. In an embodiment, the semiconductor device further comprises a source region at the first end of the stack and a drain region at the second end of the stack. In an embodiment, a gate dielectric surrounds the semiconductor channels, and a gate electrode surrounding the gate dielectric.

For example, an Electrostatically Formed Nanowire (EFN) may include a source region; at least one drain region; a wire region configured to drive a current between the source and drain regions via a conductive channel; a first lateral-gate area extending along a first surface of the wire region between the source and drain regions; a second lateral-gate area extending along a second surface of the wire region between the source and drain regions; and a sensing area in opening in a backside of a silicon substrate under the wire region and the first and second lateral-gate areas, the sensing area configured to, in reaction to a predefined substance, cause a change in a conductivity of the conductive channel.

The present disclosure relates to a semiconductor device, comprising: a groove; a first channel layer positioned within the groove; and a first barrier layer positioned within the groove, wherein a first heterojunction having a vertical interface is included between the first channel layer and the first barrier layer and 2DEG or 2DHG is formed in the first heterojunction. The present disclosure also relates to a method of manufacturing a semiconductor device.

A semiconductor device includes: a substrate; a channel layer constituted of a single nitride semiconductor on the substrate; a first barrier layer which is a nitride semiconductor on a part of an upper surface of the channel layer and having a band gap larger than that of the channel layer; a gate layer which is a nitride semiconductor on and in contact with the first barrier layer; a second barrier layer which is a nitride semiconductor in contact with the first barrier layer in an area where the gate layer is not disposed above the channel layer, and having a band gap larger than that of the channel layer and having a thickness or a band gap independent from the first barrier layer; a gate electrode on the gate layer; and a source electrode and a drain electrode spaced apart from the gate layer and on the second barrier layer.

A semiconductor device includes a first field-effect transistor positioned over a substrate, a second field-effect transistor stacked over the first field-effect transistor, a third field-effect transistor stacked over the second field-effect transistor, and a fourth field-effect transistor stacked over the third field-effect transistor. A bottom gate structure is disposed around a first channel structure of the first field-effect transistor and positioned over the substrate. An intermediate gate structure is disposed over the bottom gate structure and around a second channel structure of the second field-effect transistor and a third channel structure of the third field-effect transistor. A top gate structure is disposed over the intermediate gate structure and around a fourth channel structure of the fourth field-effect transistor. An inter-level contact is formed to bypass the intermediate gate structure from a first side of the intermediate gate structure, and arranged between the bottom gate structure and the top gate structure.

In some embodiments, the present disclosure relates to an integrated transistor device, including a first barrier layer arranged over a substrate. Further, an undoped layer may be arranged over the first barrier layer and have a n-channel device region laterally next to a p-channel device region. The n-channel device region of the undoped layer has a topmost surface that is above a topmost surface of the p-channel device region of the undoped layer. The integrated transistor device may further comprise a second barrier layer over the n-channel device region of the undoped layer. A first gate electrode is arranged over the second barrier layer, and a second gate electrode is arranged over the p-channel device region of the undoped layer.

A semiconductor device includes a support substrate having a first surface capable of supporting the epitaxial growth of at least one III-V semiconductor and a second surface opposing the first surface, at least one mesa positioned on the first surface, each mesa including an epitaxial III-V semiconductor-based multi-layer structure on the first surface of the support substrate, the III-V semiconductor-based multi-layer structure forming a boundary with the first surface and a parasitic channel suppression region positioned laterally adjacent the boundary.

A semiconductor device and a method of fabricating the same are proposed. The semiconductor device includes a plurality of hole-channel Group III nitride devices and a plurality of electron-channel Group III nitride devices. In the above, the hole-channel Group III nitride devices and the electron-channel Group III nitride devices are arranged in correspondence with each other. The electron-channel Group III nitride device has a fin-shaped channel, and a two-dimensional hole gas and/or a two-dimensional electron gas can be simultaneously formed at an interface between a compound semiconductor layer and a nitride semiconductor layer.

Semiconductor structures and methods of forming semiconductor structures that inhibit the conductivity of parasitic channels are described. In one example, a semiconductor structure includes a semiconductor substrate and a III-nitride material region over a top surface of the semiconductor substrate. The semiconductor substrate includes a bulk region below the top surface and a parasitic channel that extends to a depth from the top surface toward the bulk region of the semiconductor substrate. The parasitic channel comprises a first region and a second region. The first region of the parasitic channel comprises an implanted species having a relative atomic mass of less than 5, and the second region of the parasitic channel is free from the implanted species or the implanted species is present in the second region at a concentration that is less than in the first region.