A semiconductor device includes a substrate, a channel layer, a barrier layer, a gate, a strained layer and a passivation layer. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The gate is disposed on the barrier layer. The strained layer is disposed on the barrier layer. The passivation layer covers the gate and the strained layer. The material of the passivation layer differs from that of the strained layer.

A semiconductor device includes an underlayer made of a first nitride semiconductor, a first buffer layer made of a second nitride semiconductor, provided on the underlayer, and subjected to compressive stress from the underlayer in an in-plane direction which is perpendicular to a thickness direction of the underlayer, a second buffer layer made of a third nitride semiconductor, provided on the first buffer layer, and subjected to compressive stress from the first buffer layer in the in-plane direction, a channel layer made of a fourth nitride semiconductor, provided on the second buffer layer, and subjected to compressive stress from the second buffer layer in the in-plane direction, and a barrier layer made of a fifth nitride semiconductor, and provided above the channel layer.

A semiconductor structure includes a semiconductor substrate, a plurality of stacked units, a conductive structure, a plurality of dielectrics, a first electrode strip, a second electrode strip, and a plurality of contact structures. The stacked units are stacked up over the semiconductor substrate, and comprises a first passivation layer, a second passivation layer and a channel layer sandwiched between the first passivation layer and the second passivation layer. The conductive structure is disposed on the semiconductor substrate and wrapping around the stacked units. The dielectrics are surrounding the stacked units and separating the stacked units from the conductive structure. The first electrode strip and the second electrode strip are located on two opposing sides of the conductive structure. The contact structures are connecting the channel layer of each of the stacked units to the first electrode strip and the second electrode strip.

A semiconductor device includes first and second nitride semiconductor layers, a source, a drain, a gate structure, first and second p-type doped nitride semiconductor compound islands. The second nitride semiconductor layer is disposed on the first nitride semiconductor layer and has a bandgap greater than that of the first nitride semiconductor layer. The source, the drain, and the gate structure are disposed on the second nitride semiconductor layer. The drain viewed in a direction normal to the second nitride semiconductor layer extends longitudinally in an extending direction. The gate structure is between the source and the drain. The first p-type doped nitride semiconductor compound islands are disposed on the second nitride semiconductor layer and arranged adjacent to the drain along the extending direction. The second p-type doped nitride semiconductor compound island is disposed between the gate structure and the second nitride semiconductor layer.

A semiconductor field-effect transistor, a power amplifier comprising the same and a manufacturing method thereof are provided herein. The semiconductor field-effect transistor contains an n-type doped layer arranged close to the edge of the two-dimensional electron gas area in a channel layer; said n-type doped layer is arranged to adjust the distribution of electron concentration in the transistor, and to improve the RF linearity of the overall component; thereby not only the threshold voltage can be controlled through the adjustment of the charge, but the contact and series resistance can also be reduced.

An improved high electron mobility transistor (HEMT) structure includes in order a substrate, a nucleation layer, a buffer layer, a channel layer, and a barrier layer, wherein the buffer layer includes a dopant. The channel layer having a dopant doping concentration less than that of the buffer layer. A two-dimension electron gas is formed in the channel layer along an interface between the channel layer and the barrier layer. A dopant doping concentration of the channel layer at an interface between the channel layer and the barrier layer is equal to or greater than 1×10.sup.15 cm.sup.−3.

An improved high electron mobility transistor (HEMT) structure includes a substrate, a nitride nucleation layer, a nitride buffer layer, a nitride channel layer, and a barrier layer. The nitride buffer layer includes a metal dopant. The nitride channel layer has a metal doping concentration less than that of the nitride buffer layer. A two-dimensional electron gas is formed in the nitride channel layer along an interface between the nitride channel layer and the barrier layer. A metal doping concentration X at an interface between the nitride buffer layer and the nitride channel layer is defined as the number of metal atoms per cubic centimeter, and a thickness Y of the nitride channel later is in microns (μm) and satisfies Y≤(0.2171)ln(X)−8.34, thereby reducing an influence of the metal dopant to a sheet resistance value of the nitride channel layer and providing the improved HEMT structure having a better performance.

Semiconductor structures and methods of forming semiconductor structures that inhibit the conductivity of parasitic channels are described. In one example, a semiconductor structure includes a semiconductor substrate and a III-nitride material region over a top surface of the semiconductor substrate. The semiconductor substrate includes a bulk region below the top surface and a parasitic channel that extends to a depth from the top surface toward the bulk region of the semiconductor substrate. The parasitic channel comprises a first region and a second region. The first region of the parasitic channel comprises an implanted species having a relative atomic mass of less than 5, and the second region of the parasitic channel is free from the implanted species or the implanted species is present in the second region at a concentration that is less than in the first region.

In some examples, a transistor comprises a gallium nitride (GaN) layer; a GaN-based alloy layer having a top side and disposed on the GaN layer, wherein source, drain, and gate contact structures are supported by the GaN layer; and a first doped region positioned in a drain access region and extending from the top side into the GaN layer.

A semiconductor structure includes a semiconductor substrate, a plurality of stacked units, a conductive structure, a plurality of dielectrics, a first electrode strip, a second electrode strip, and a plurality of contact structures. The stacked units are stacked up over the semiconductor substrate, and comprises a first passivation layer, a second passivation layer and a channel layer sandwiched between the first passivation layer and the second passivation layer. The conductive structure is disposed on the semiconductor substrate and wrapping around the stacked units. The dielectrics are surrounding the stacked units and separating the stacked units from the conductive structure. The first electrode strip and the second electrode strip are located on two opposing sides of the conductive structure. The contact structures are connecting the channel layer of each of the stacked units to the first electrode strip and the second electrode strip.