An epitaxial structure for a high-electron-mobility transistor includes a substrate, a nucleation layer, a buffer layered unit, a channel layer, and a barrier layer sequentially stacked on one another in such order. The buffer layered unit includes at least one multiple quantum well structure containing a plurality of p-i-n heterojunction stacks. Each of the p-i-n heterojunction stacks includes p-type, i-type, and n-type layers which are alternately stacked along a direction away from the nucleation layer, and which are made of materials respectively represented by chemical formulas of Al.sub.xGa.sub.(1-x)N, Al.sub.yGa.sub.(1-y)N, and Al.sub.zGa.sub.(1-z)N. For each of the p-i-n heterojunction stacks, x gradually decreases and z gradually increases along the direction away from the nucleation layer, and y is consistent and ranges from 0 to 0.7.

An apparatus configured to reduce lag includes a substrate; a group III-Nitride back barrier layer on the substrate; a group III-Nitride channel layer on the group III-Nitride back barrier layer; a group III-Nitride barrier layer on the group III-Nitride channel layer, the group III-Nitride barrier layer include a higher bandgap than a bandgap of the group III-Nitride channel layer; a source electrically coupled to the group III-Nitride barrier layer; a gate on the group III-Nitride barrier layer; a drain electrically coupled to the group III-Nitride barrier layer; and a p-region being arranged at or below the group III-Nitride barrier layer. Additionally, at least a portion of the p-region is arranged vertically below at least one of the following: the source, the gate, an area between the gate and the drain.

An apparatus for reducing lag includes a substrate; a group III-Nitride barrier layer; a source electrically coupled to the group III-Nitride barrier layer; a gate on the group III-Nitride barrier layer; a drain electrically coupled to the group III-Nitride barrier layer; a p-region being arranged at or below the group III-Nitride barrier layer; and a gate control circuit configured to control a gate voltage of the gate. Additionally, at least a portion of the p-region is arranged vertically below at least one of the following: the source, the gate, and an area between the gate and the drain.

One or more semiconductor structures comprising a hole draining structure are provided. A semiconductor structure has a first layer formed over a substrate. The first layer has a first concentration of a metal material. The semiconductor structure has a second layer formed over the first layer. The second layer has a second concentration of the metal material different than the first concentration of the metal material. The semiconductor structure has a hole draining structure formed from a superlattice formed between the first layer and the second layer. The hole draining structure has a concentration of the metal material increasing towards the first layer and decreasing towards the second layer.

A superlattice structure includes a substrate. A first superlattice stack is disposed on the substrate. The first superlattice stack includes a first superlattice layer, a second superlattice layer and a third superlattice layer disposed from bottom to top. Three stress relaxation layers respectively disposed between the first superlattice layer and the second superlattice layer, the second superlattice layer and the third superlattice layer and on the third superlattice layer. Each of the stress relaxation layers includes a group III-V compound layer. The thickness of each of the stress relaxation layers should be greater than a relaxation critical thickness.

A nitride semiconductor device includes: a diamond substrate; a first graphene layer provided on the diamond substrate; a second graphene layer provided on the first graphene layer; a nitride semiconductor layer provided on the second graphene layer; and a nitride semiconductor element having an electrode provided on the nitride semiconductor layer, wherein the first and second graphene layers are provided as an interface layer between the diamond substrate and the nitride semiconductor layer.

A semiconductor device includes a substrate having an upper surface including a recess region, a semiconductor structure on the substrate, a portion of the semiconductor structure within the recess region, and a gate contact, a drain contact, and a source contact on the semiconductor structure. The recess region does not vertically overlap the drain contact or the source contact.

A semiconductor device manufacturing method of embodiments includes: performing first ion implantation implanting an element of either carbon (C) or oxygen (O) into a nitride semiconductor layer; performing second ion implantation implanting hydrogen (H) into the nitride semiconductor layer; forming a coating layer on a surface of the nitride semiconductor layer; performing a first heat treatment; removing the coating layer; and performing a second heat treatment.

A semiconductor device includes a substrate, a nucleation layer, a buffer layer, first and second nitride-based semiconductor layers, a pair of S/D electrodes, and a gate electrode. The nucleation layer is disposed on the substrate. The buffer layer includes a III-V compound which includes a first element. The buffer layer is disposed on the nucleation layer. The buffer layer has a variable concentration of the first element that incrementally increases and then decrementally decreases as a function of a distance within a thickness of the buffer layer. The first nitride-based semiconductor layer is disposed on the buffer layer. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer and has a bandgap greater than a bandgap of the first nitride-based semiconductor layer. The S/D electrodes and a gate electrode are disposed over the second nitride-based semiconductor layer.

Provided are a semiconductor substrate and a transistor. The semiconductor substrate includes a base, an insulating layer, a semiconductor layer, a wide bandgap diffusion buffer layer and a nucleation layer. The insulating layer is disposed on the base. The semiconductor layer is disposed on the insulating layer. The wide bandgap diffusion buffer layer is disposed on the semiconductor layer, wherein the bandgap of the wide bandgap buffer diffusion layer is higher than 2.5 eV. The nucleation layer is disposed on the wide bandgap diffusion buffer layer, wherein the nucleation layer includes an aluminum-containing layer.