A semiconductor structure includes a seed layer on a substrate and an epitaxial stack on the seed layer. The epitaxial stack includes a first superlattice part and a second superlattice part on the first superlattice part. The first superlattice part includes first units repetitively stacked M1 times on the seed layer. Each first unit includes a first sub-layer that is an Al.sub.y1Ga.sub.1-y1N layer, and a second sub-layer that is an Al.sub.x1Ga.sub.1-x1N layer, wherein y1<x1. The second superlattice part includes second units repetitively stacked M2 times on the first superlattice part. Each second unit includes a third sub-layer that is an Al.sub.y2Ga.sub.1-y2N layer, and a fourth sub-layer that is an Al.sub.x2Ga.sub.1-x2N layer, wherein y2<x2. M1 and M2 are positive integers, 0≤x1, y1 and y2<1, 0<x2≤1, and x1<x2, or x1=x2 and y1<y2.

Some embodiments of the disclosure provide a semiconductor device. The semiconductor device includes: a doped substrate; a barrier layer, disposed on the doped substrate; a channel layer, disposed between the doped substrate and the barrier layer; and a doped semiconductor structure, disposed in the doped substrate, where a band gap of the barrier layer is greater than a band gap of the channel layer, the doped substrate and the doped semiconductor structure have different polarities, and the doped substrate includes a doped silicon substrate.

A semiconductor device includes a substrate, a relaxation layer, a channel layer, a polarization compensation layer, and a barrier layer. The relaxation layer is over the substrate and configured to reduce a total strain of the semiconductor device. The channel layer is over the relaxation layer. The polarization compensation layer is between the relaxation layer and the channel layer and configured to reduce a polarization between the relaxation layer and the channel layer. The barrier layer is over the relaxation layer and configured to polarize a junction between the barrier layer and the channel layer to induce a two-dimensional electron gas in the channel layer.

A layer structure for a normally-off transistor has an electron-supply layer made of a group-III-nitride material, a back-barrier layer made of a group-III-nitride material, a channel layer between the electron-supply layer and the back-barrier layer, made of a group-III-nitride material having a band-gap energy that is lower than the band-gap energies of the other layer mentioned. The material of the back-barrier layer is of p-type conductivity, while the material of the electron-supply layer and the material of the channel layer are not of p-type conductivity, the band-gap energy of the electron-supply layer is smaller than the band-gap energy of the back-barrier layer. In absence of an external voltage a lower conduction-band-edge of the third group-III-nitride material in the channel layer is higher in energy than a Fermi level of the material in the channel layer.

An epitaxial wafer including: a silicon-based substrate; a first buffer layer on the substrate and including a first multilayer structure buffer region composed of Al.sub.xGa.sub.1-xN layers and Al.sub.yGa.sub.1-yN layers (x>y) alternately disposed and a first insertion layer composed of an Al.sub.zGa.sub.1-zN layer (x>z) and is thicker than the Al.sub.yGa.sub.1-yN layer, the first regions and insertion layers alternately disposed; a second buffer layer on the first and including a second multilayer structure buffer region composed of Al.sub.αGa.sub.1-αN layers and Al.sub.βGa.sub.1-βN layers (α>β) alternately disposed and a second insertion layer composed of an Al.sub.γGa.sub.1-γN layer (α>γ) and is thicker than the Al.sub.βGa.sub.1-βN layer, the second regions and insertion layers alternately disposed; and a channel layer on the second buffer layer and thicker than the second insertion layer. The average Al composition in the second buffer layer is higher than that in the first.

A High Electron Mobility Transistor (HEMT) made of nitride semiconductor materials and a process of forming the same are disclosed. The HEMT has a feature that an n-type layer doped with n-type dopants is provided between the buffer layer and the channel layer. The existence of the n-type layer with a substantial conductance beneath the channel layer suppresses the current collapsing and enhances the surface quality of the channel layer in spite of a thinned channel layer.

A semiconductor device includes a substrate and a first III-V compound layer disposed on the substrate. The first III-V compound layer includes a plurality of crystal lattices, each of which has a prism plane. The semiconductor device further includes a second III-V compound layer disposed on the first III-V compound layer. The semiconductor device includes a source electrode, a drain electrode and a gate electrode disposed on the second III-V compound layer. The source electrode and the drain electrode define a channel region that has a plurality of channels of charge carriers in the first III-V compound layer. The normal direction of the prism plane defines an m-axis, and each of the channels of the charge carriers is parallel with the m-axis.

The present disclosure is related to a III-Nitride semiconductor device comprising a base substrate, a buffer layer, a channel layer, a barrier layer so that a 2-dimensional charge carrier gas is formed or can be formed near the interface between the channel layer and the barrier layer, and at least one set of a first and second electrode in electrical contact with the 2-dimensional charge carrier gas, wherein the device further comprises a mobile charge layer (MCL) within the buffer layer or near the interface between the buffer layer and the channel layer, when the device is in the on-state. The device further comprises an electrically conductive path between one of the electrodes and the mobile charge layer. The present disclosure is also related to a method for producing a device according to the present disclosure.

Disclosed is an enhancement-mode semiconductor device, comprising: a substrate; a p-type semiconductor layer, the p-type semiconductor layer being disposed on the substrate; an n-type semiconductor layer, the n-type semiconductor layer being disposed on the p-type semiconductor layer, a groove being formed in a gate region of the n-type semiconductor layer, and the first groove penetrating the n-type semiconductor layer; a channel layer, the channel layer being conformally disposed on the n-type semiconductor layer and in the first groove; and a barrier layer, the barrier layer being conformally disposed on the channel layer. The enhancement-mode semiconductor device has a simple structure, a good repeatability, and avoids bringing impurities and defects to the channel layer and the barrier layer.

Disclosed is an enhancement-mode semiconductor device, comprising: a substrate; a p-type nitride semiconductor layer and an n-type nitride semiconductor layer formed on the substrate in sequence, the p-type nitride semiconductor layer having a first protruding structure at a gate region of the p-type nitride semiconductor layer; the n-type nitride semiconductor layer having a first through hole corresponding to the first protruding structure, exposing the gate region of the p-type nitride semiconductor layer; a channel layer conformally disposed on the n-type semiconductor layer and the first protruding structure; a barrier layer, the barrier layer being conformally disposed on the channel layer. The enhancement-mode semiconductor device has a simple structure, a good repeatability, and avoids impurities and defects brought to the channel layer and the barrier layer.