Monolithic microwave integrated circuits (MMICs) tolerant to electrical overstress are provided. In certain embodiments, a MMIC includes a signal pad that receives a radio frequency (RF) signal, and an RF circuit coupled to the RF signal pad. The RF circuit includes a transistor layout, an input field-effect transistor (FET) implemented using a first portion of a plurality of gate fingers of the transistor layout, and an embedded protection device electrically connected between a gate and a source of the input FET and implemented using a second portion of the plurality of gate fingers. The MMIC is tolerant to electrical overstress events, such as field-induced charged-device model (FICDM) events.

Monolithic microwave integrated circuits (MMICs) tolerant to electrical overstress are provided. In certain embodiments, a MMIC includes a signal pad that receives a radio frequency (RF) signal, and an RF circuit coupled to the RF signal pad. The RF circuit includes a transistor layout, an input field-effect transistor (FET) implemented using a first portion of a plurality of gate fingers of the transistor layout, and an embedded protection device electrically connected between a gate and a source of the input FET and implemented using a second portion of the plurality of gate fingers. The MMIC is tolerant to electrical overstress events, such as field-induced charged-device model (FICDM) events.

A semiconductor device includes a nitride semiconductor laminated structure formed on a substrate, a source electrode formed on the nitride semiconductor laminated structure, a drain electrode and a gate electrode, and a surface protection film covering the nitride semiconductor laminated structure. the nitride semiconductor laminated structure includes: a first nitride semiconductor layer formed on the substrate; and a second nitride semiconductor layer formed on the first nitride semiconductor layer and having a composition different from the first nitride semiconductor layer. The surface protection film includes: a first insulating film formed to have contact with the gate electrode; and a second insulating film formed adjacent to the first insulating film and having a higher carbon concentration than the first insulating film.

A semiconductor device includes a nitride semiconductor laminated structure formed on a substrate, a source electrode formed on the nitride semiconductor laminated structure, a drain electrode and a gate electrode, and a surface protection film covering the nitride semiconductor laminated structure. the nitride semiconductor laminated structure includes: a first nitride semiconductor layer formed on the substrate; and a second nitride semiconductor layer formed on the first nitride semiconductor layer and having a composition different from the first nitride semiconductor layer. The surface protection film includes: a first insulating film formed to have contact with the gate electrode; and a second insulating film formed adjacent to the first insulating film and having a higher carbon concentration than the first insulating film.

A semiconductor device includes a channel layer, a barrier layer, and at least one contact layer. The channel layer includes a GaN-based material. The barrier layer includes an AlInN-based material in which a composition ratio of In is higher than 18%, and is provided on the channel layer. The at least one contact layer includes a conductive-type semiconductor material and is provided to penetrate the barrier layer and reach the channel layer.

A semiconductor device includes a channel layer, a barrier layer, and at least one contact layer. The channel layer includes a GaN-based material. The barrier layer includes an AlInN-based material in which a composition ratio of In is higher than 18%, and is provided on the channel layer. The at least one contact layer includes a conductive-type semiconductor material and is provided to penetrate the barrier layer and reach the channel layer.

Provided are a Schottky diode and a manufacturing method therefor. The Schottky diode (100) includes a nitride channel layer (1); a nitride barrier layer (2) formed on the nitride channel layer (1); a nitride cap layer (3) formed on the nitride barrier layer (2), wherein the nitride cap layer (3) includes an active region (31) and an inactive region (32); a passivation layer (4) formed on the nitride cap layer (3), where the passivation layer (4) includes a first groove penetrating through the passivation layer (4) to expose the nitride cap layer (3), and the first groove corresponds to the active region (31); a dielectric layer (5) located on the passivation layer (4) and an inner wall of the first groove, wherein the dielectric layer (5) forms a second groove, and the dielectric layer (5) includes a third groove penetrating through the dielectric layer (5) to expose a part of the active region (31) of the nitride cap layer (3); and an anode layer (6) formed in the second groove and the third groove and in contact with the active region (31).

A high electron mobility transistor and a method of manufacturing the same are disclosed. The high electron mobility transistor includes a channel layer, a channel supplying layer causing generation of a two-dimensional electron gas (2DEG) in the channel layer, a source electrode and a drain electrode provided on respective sides of the channel supplying layer, a depletion forming layer provided on the channel supplying layer to form a depletion region in the 2DEG, a gate electrode provided on a portion of the depletion forming layer, and a current limiting layer provided to contact the gate electrode on another portion of the depletion forming layer. The current limiting layer limits a current flow from the gate electrode to the depletion forming layer according to a voltage applied to the gate electrode.

A high electron mobility transistor and a method of manufacturing the same are disclosed. The high electron mobility transistor includes a channel layer, a channel supplying layer causing generation of a two-dimensional electron gas (2DEG) in the channel layer, a source electrode and a drain electrode provided on respective sides of the channel supplying layer, a depletion forming layer provided on the channel supplying layer to form a depletion region in the 2DEG, a gate electrode provided on a portion of the depletion forming layer, and a current limiting layer provided to contact the gate electrode on another portion of the depletion forming layer. The current limiting layer limits a current flow from the gate electrode to the depletion forming layer according to a voltage applied to the gate electrode.

The present disclosure provides a high electron mobility transistor including a channel layer; a barrier layer on the channel layer and configured to induce formation of a 2-dimensional electron gas (2DEG) to the channel layer; a p-type semiconductor layer on the barrier layer; a first passivation layer on the barrier layer and including a quaternary material of Al, Ga, O, and N; a gate electrode on the p-type semiconductor layer; and a source electrode and a drain electrode provided on both sides of the barrier layer and separated from the gate electrode.