Coupled polysilicon guard rings for enhancing breakdown voltage in a power semiconductor device are presented herein. Polysilicon guard rings are disposed above the power device drift region and electrically coupled to power device regions (e.g., device diffusions) so as to spread electric fields associated with an operating voltage. Additionally, PN junctions (i.e., p-type and n-type junctions) are formed within the polysilicon guard rings to operate in reverse bias with a low leakage current between the power device regions (e.g., device diffusions). Low leakage current may advantageously enhance the electric field spreading without deleteriously affecting existing (i.e., normal) power device performance; and enhanced electric field spreading may in turn reduce breakdown-voltage drift.

RF transistor amplifiers include an RF transistor amplifier die having a Group III nitride-based semiconductor layer structure and a plurality of gate terminals, a plurality of drain terminals, and at least one source terminal that are each on an upper surface of the semiconductor layer structure, an interconnect structure on an upper surface of the RF transistor amplifier die, and a coupling element between the RF transistor amplifier die and the interconnect structure that electrically connects the gate terminals, the drain terminals and the source terminal to the interconnect structure.

A radio frequency (RF) switch is provided. The RF switch is configured to switch a RF signal input to a first terminal. The RF switch includes a first transistor, disposed at a first distance from the first terminal, and configured to switch the RF signal, and a second transistor, disposed at a second distance from the first terminal, and configured to switch the RF signal. The first distance is shorter than the second distance, and a number of first contact vias formed in a first electrode in the first transistor is greater than a number of second contact vias formed in a second electrode of the second transistor.

A nitride semiconductor transistor device is disclosed. The device includes a first nitride semiconductor layer disposed over a substrate, and a second nitride semiconductor layer with a band gap larger than the first nitride semiconductor disposed over the first nitride semiconductor layer. Over the second nitride semiconductor layer, a first insulating film, a charge-storing gate electrode, a second insulating film, and a second gate electrode are formed in order thereon. A source electrode and a drain electrode are disposed over the second nitride semiconductor layer interposing the charge-storing gate electrode in a plane direction. The device further includes a first gate electrode capacitively coupling with the charge-storing gate electrode with an insulating film therebetween forming a first capacitor, and the charge-storing gate electrode is charged by an electron injection from the first gate electrode through the first capacitor.

A heterojunction device, includes a substrate; a III-nitride semiconductor region located longitudinally above or over the substrate and including a heterojunction having a two-dimensional carrier gas; first and second laterally spaced terminals operatively connected to the semiconductor; a gate structure of first conductivity type located above or longitudinally over the semiconductor region and laterally spaced between the first and second terminals; a control gate terminal operatively connected to the gate structure, a potential applied to the control gate terminal modulates and controls a current flow through the carrier gas between the terminals, the carrier gas being a second conductivity type; an injector of carriers of the first conductivity type laterally spaced away from the second terminal; and a floating contact layer located over the carrier gas and laterally spaced away from the second terminal and operatively connected to the injector and the semiconductor region.

Examples of integrated semiconductor devices are described. In one example, an integrated device includes first and second transistors formed on a substrate, where the transistors share a terminal metal feature to reduce a size of the integrated device. The terminal metal feature can include a shared source electrode metalization, for example, although other electrode metalizations can be shared. In other aspects, a first width of a gate of the first transistor can be greater than a second width of a gate of the second transistor, and the shared metalization can taper from the first width to the second width. The integrated device can also include a metal ground plane on a backside of the substrate, and the terminal metal feature can also include an in-source via for the shared source electrode metalization. The in-source via can electrically couple the shared source electrode metalization to the metal ground plane.

Because of inclusion of: a source electrode that is formed on a front surface of a semiconductor substrate and that is joined to the semiconductor substrate both at a source electrode as a first contact region that is an ohmic contact region and at a source electrode as a second contact region that is a contact region with a non-ohmic contact or the like; a back-surface electrode formed on a back surface of the semiconductor substrate; and a through hole in which an interconnection is provided that connects the source electrode as the second contact region in the source electrode with the back-surface electrode; it is possible not only to improve the corrosion resistance but also to reduce the leakage current, so that a highly-reliable semiconductor device suited for high frequency operation is provided.

An electrostatic discharge protection structure for a nitride-based device having an active region, an electrostatic discharge protection region outside the active region for forming the electrostatic discharge protection structure, and a field plate formed in the active region is provided. The electrostatic discharge protection structure includes a channel layer, and a barrier layer, a first p-type nitride layer and a metal layer formed on the channel layer in such order. The metal layer is electrically connected to the field plate in the active region. A nitride-based device having the electrostatic discharge protection structure and a method for manufacturing a nitride-based device is also disclosed.

A semiconductor device includes a semiconductor layer that has a transistor structure including a p type source region, a p type drain region, an n type body region between the p type source region and the p type drain region, and a gate electrode facing the n type body region and a voltage-regulator diode that is disposed at the semiconductor layer and that has an n type portion connected to the p type source region and a p type portion connected to the gate electrode, in which the transistor structure and the voltage-regulator diode are unified into a single-chip configuration.

A semiconductor device includes a first nitride semiconductor layer; a second nitride semiconductor layer provided on the first nitride semiconductor layer and having a bandgap larger than a bandgap of the first nitride semiconductor layer; a nitride insulating layer provided between the first nitride semiconductor layer and the second nitride semiconductor layer; a plurality of first drain electrodes each having a part provided on the nitride insulating layer and a part provided beneath the nitride insulating layer; a plurality of second drain electrodes each having a part provided on the nitride insulating layer and a part provided beneath the nitride insulating layer; a plurality of third drain electrodes each having a part provided on the nitride insulating layer and a part provided beneath the nitride insulating layer; a plurality of fourth drain electrodes each having a part provided on the nitride insulating layer and a part provided beneath the nitride insulating layer; a plurality of first source electrodes provided between the first drain electrodes and the third drain electrodes, the first source electrodes each having a part provided on the nitride insulating layer and a part provided beneath the nitride insulating layer; and a plurality of second source electrodes provided between the first drain electrodes and the third drain electrodes, the second source electrodes each having a part provided on the nitride insulating layer and a part provided beneath the nitride insulating layer. The first drain electrodes are separated from each other by a first distance in a first direction parallel to an interface between the first nitride semiconductor layer and the nitride insulating layer. The second drain electrodes are separated from each other by a second distance in the first direction and positioned from the first drain electrodes by a third distance in the first direction and positioned from the first drain electrodes by a fourth distance in a second direction intersecting with the first direction and parallel to the interface and electrically connected to the first drain electrodes. The third drain electrodes are separated from each other by a fifth distance in the first direction and separated from the first drain electrodes and the second drain electrodes in the second direction. The fourth drain electrodes are separated from each other by a sixth distance in the first direction and positioned from the third drain electrodes by a seventh distance in the first direction and positioned from the third drain electrodes by an eighth distance in the second direction and separated from the first drain electrodes and the second drain electrodes and e