A semiconductor device is provided. The semiconductor device includes a substrate, a fin structure and an epitaxial source/drain structure. The substrate includes a substrate layer and an insulator layer on the substrate layer. The fin structure is formed over the substrate, wherein the fin structure includes a gate structure and channel layers wrapped by the gate structure. The epitaxial source/drain structure is connected to the channel layers, wherein a bottom portion of the epitaxial source/drain structure is in contact with the insulator layer of the substrate.

A semiconductor device may include a substrate including a first cell region, a second cell region, and a dummy region between the first and second cell regions, and conductive patterns included in the first cell region, the second cell region, and the dummy region. A first pattern density, which is defined as a density of the conductive patterns of the first cell region, may be different from a second pattern density, which is defined as a density of the conductive patterns of the second cell region. A third pattern density, which is defined as a density of the conductive patterns of the dummy region, gradually changes in a region between the first cell region and the second cell region. A top surface of the substrate may be inclined at an angle, in the dummy region.

The present disclosure describes a method to form a semiconductor device with backside contact structures. The method includes forming a semiconductor device on a first side of a substrate. The semiconductor device includes a source/drain (S/D) region. The method further includes etching a portion of the S/D region on a second side of the substrate to form an opening and forming an epitaxial contact structure on the S/D region in the opening. The second side is opposite to the first side. The epitaxial contact structure includes a first portion in contact with the S/D region in the opening and a second portion on the first portion. A width of the second portion is larger than the first portion.

A semiconductor device structure includes a first S/D feature over a first device region of a substrate, a plurality of first semiconductor layers over the first device region of the substrate, and each first semiconductor layer is in contact with the first source/drain feature, a first gate electrode layer surrounding a portion of each first semiconductor layer, and a first dielectric spacer contacting the first S/D feature, the first dielectric spacer disposed between and in contact with two first semiconductor layers of the plurality of the first semiconductor layers. The substrate comprises a first dopant region underneath the first S/D feature and a second dopant region underneath first gate electrode layer and radial outwardly of the first dopant region, the first dopant region comprising first dopants having a first conductivity type and a first dopant concentration and the second dopant region comprising the first dopants having a second dopant concentration less than the first dopant concentration.

An integrated circuit includes a nanosheet transistor having a plurality of stacked channels, a gate electrode surrounding the stacked channels, a source/drain region, and a source/drain contact. The integrated circuit includes a first dielectric layer between the gate metal and the source/drain contact, a second dielectric layer on the first dielectric layer, and a cap metal on the first gate metal and on a hybrid fin structure. The second dielectric layer is on the hybrid fin structure between the cap metal and the source/drain contact.

A semiconductor device structure and a method for forming a semiconductor device structure are provided. The semiconductor device structure includes a stack of channel structures over a semiconductor fin and a gate stack wrapped around the channel structures. The semiconductor device structure also includes a source/drain epitaxial structure adjacent to the channel structures and multiple inner spacers. Each of the inner spacers is between the gate stack and the source/drain epitaxial structure. The semiconductor device structure further includes an isolation structure between the semiconductor fin and the source/drain epitaxial structure.

According to an embodiment of a semiconductor device, the semiconductor device includes: a first active cell area comprising a first plurality of parallel gate trenches; a second active cell area comprising a second plurality of parallel gate trenches; and a metallization layer above the first and the second active cell areas. The metallization layer includes: a first part contacting a semiconductor mesa region between the plurality of parallel gate trenches in the first and the second active cell areas; and a second part surrounding the first part. The second part of the metallization layer contacts the first plurality of gate trenches along a first direction and the second plurality of gate trenches along a second direction different from the first direction.

Methods of forming a self-aligned gate (SAG) and self-aligned source (SAD) device for high E.sub.crit semiconductors are presented. A dielectric layer is deposited on a high E.sub.crit substrate. The dielectric layer is etched to form a drift region. A refractory material is deposited on the substrate and dielectric layer. The refractory material is etched to form a gate length. Implant ionization is applied to form high-conductivity and high-critical field strength source with SAG and SAD features. The device is annealed to activate the contact regions. Alternately, a refractory material may be deposited on a high E.sub.crit substrate. The refractory material is etched to form a channel region. Implant ionization is applied to form high-conductivity and high E.sub.crit source and drain contact regions with SAG and SAD features. The refractory material is selectively removed to form the gate length and drift regions. The device is annealed to activate the contact regions.

A semiconductor device includes an active region on a substrate, a gate structure on the substrate and intersecting the active region, a source/drain region on the active region on both sides of the gate structure and including silicon (Si), and a contact structure on the source/drain region. The source/drain region includes a shallow doping region doped with germanium (Ge) and is in an upper region including an upper surface of the source/drain region. A concentration of germanium (Ge) in the shallow doping region gradually decreases from the upper surface of the source/drain region toward an upper surface of the substrate in a direction that is perpendicular to an upper surface of the substrate.

A semiconductor structure includes a substrate, a passive device and an active device over the substrate. The active device is formed in the first region of the substrate, and the passive device is formed in the second region of the substrate. The semiconductor structure further includes a passivation layer that covers the top surface of the passive device. The passivation layer has an opening that exposes the active device.