A semiconductor device and method of forming thereof includes a first fin and a second fin each extending from a substrate. A first gate segment is disposed over the first channel and a second gate segment is disposed over the second channel. An interlayer dielectric (ILD) layer is adjacent the first gate segment and the second gate segment. A cut region (e.g., opening or gap between first gate structure and the second gate structure) extends between the first and second gate segments. The cut region has a first portion has a first width and a second portion has a second width, the second width is greater than the first width. The second portion interposes the first and second gate segments and the first portion is defined within the ILD layer.

A field effect transistor includes a substrate and spacers over the substrate. The field effect transistor includes a channel recess cavity between the spacers, wherein a bottom-most surface of the channel recess cavity is parallel to the substrate top surface. The field effect transistor includes a gate stack, wherein the gate stack includes a bottom portion in the channel recess cavity and a top portion outside the channel recess cavity, the gate stack further includes a gate dielectric layer extending from the channel recess cavity along sidewalls of each of the pair of spacers, and the gate dielectric layer directly contacts the substrate below substrate top surface. The field effect transistor includes a strained source/drain (S/D) below the substrate top surface, wherein the strained S/D extends below the gate stack. The field effect transistor further includes a source/drain (S/D) extension substantially conformably surrounding the strained S/D.

Some embodiments include a memory cell having a conductive gate comprising ruthenium. A charge-blocking region is adjacent the conductive gate, a charge-storage region is adjacent the charge-blocking region, a tunneling material is adjacent the charge-storage region, and a channel material is adjacent the tunneling material. Some embodiments include an assembly having a vertical stack of alternating insulative levels and wordline levels. The wordline levels contain conductive wordline material which includes ruthenium. Semiconductor material extends through the stack as a channel structure. Charge-storage regions are between the conductive wordline material and the channel structure. Charge-blocking regions are between the charge-storage regions and the conductive wordline material. Some embodiments include methods of forming integrated assemblies.

Gate structures having neutral zones to minimize metal gate boundary effects and methods of fabricating thereof are disclosed herein. An exemplary metal gate includes a first portion, a second portion, and a third portion. The second portion is disposed between the first portion and the third portion. The first portion includes a first gate dielectric layer, a first p-type work function layer, and a first n-type work function layer. The second portion includes a second gate dielectric layer and a second p-type work function layer. The third portion includes a third gate dielectric layer, a third p-type work function, and a second n-type work function layer. The second p-type work function layer separates the first n-type work function layer from the second n-type work function layer, such that the first n-type work function layer does not share an interface with the second n-type work function layer.

A transistor includes a substrate including a P-type-sub region doped with P-type impurities, a well region positioned at an upper portion of the substrate and doped with P-type impurities, a gate structure on the well region, and drain and source regions. The gate structure includes a gate insulation layer, first and second conductive patterns for adjusting a threshold voltage and a gate electrode. The drain and source regions are positioned at an upper portion of the substrate adjacent first and second sidewalk of the gate structure, respectively. The source region is doped with N-type impurities. The drain region includes a highly doped N-type impurity region, an N-type impurity region, and a lightly doped P-type impurity region sequentially disposed in a downward direction from a top surface of the substrate. A boundary between the well region and the P-type sub region is positioned under a bottom of the drain region.

A semiconductor device includes a first source/drain region and a second source/drain region disposed in a semiconductor substrate. The semiconductor device also includes a word line structure disposed in the semiconductor substrate and between the first source/drain region and the second source/drain region. The word line structure includes a composite gate dielectric, and a lower electrode layer disposed over the composite gate dielectric. The word line structure also includes an upper electrode layer disposed over the lower electrode layer, and a graphene layer disposed between the lower electrode layer and the upper electrode layer. The composite gate dielectric includes a gate dielectric layer and a protection liner.

A semiconductor device includes a first channel region disposed over a substrate, and a first gate structure disposed over the first channel region. The first gate structure includes a gate dielectric layer disposed over the channel region, a lower conductive gate layer disposed over the gate dielectric layer, a ferroelectric material layer disposed over the lower conductive gate layer, and an upper conductive gate layer disposed over the ferroelectric material layer. The ferroelectric material layer is in direct contact with the gate dielectric layer and the lower gate conductive layer, and has a U-shape cross section.

The present disclosure provides a method of manufacturing a semiconductor device. The method includes steps of providing a patterned mask having a plurality of openings on a substrate; etching the substrate through the openings to form an etched substrate and a trench in the etched substrate, wherein the etched substrate comprises a protrusion; introducing dopants having a first conductivity type in the etched substrate and on either side of the trench to form a plurality of first impurity regions; forming an isolation film in the trench; and depositing a conductive material on the isolation film.

A semiconductor structure includes a substrate, a first word line structure, a second word line structure, a third word line structure, and a fourth word line structure. The substrate has an active region surrounded by an isolation structure. The first and second word line structures are disposed in the active region and separated from each other. The third and fourth word line structures are disposed in the isolation structure, and each of the third and the fourth word line structures includes a bottom work-function layer, a middle work-function layer on the bottom work-function layer, and a top work function layer on the work-function middle layer. The middle work-function layer has a work-function that is higher than a work-function of the top work-function layer and a work-function of the bottom work-function layer.

Some embodiments of the present invention include apparatuses and methods relating to NMOS and PMOS transistor strain.