A multilayer graphene composite comprising a plurality of stacked graphene layers separated from one another by an ion gel, wherein the ion gel is intercalated between adjacent graphene layers such that ions within the ion gel are able to arrange themselves at the surfaces of the graphene layers to cause a detectable change in one or more of an electrical and optical property of the graphene layers when a gate voltage is applied to a gate electrode in proximity to the ion gel.

A device includes a substrate, a first electrode on the substrate, an insulating pattern on the substrate, a second electrode on an upper end of the insulating pattern, a two-dimensional (2D) material layer on a side surface of the insulating pattern, a gate insulating layer covering the 2D material layer, and a gate electrode contacting the gate insulting layer. The insulating pattern extends from the first electrode in a direction substantially vertical to the substrate. The 2D material layer includes at least one atomic layer of a 2D material that is substantially parallel to the side surface of the insulating pattern.

A semiconductor device of the present invention includes a gate electrode buried in a gate trench of a first conductivity-type semiconductor layer, a first conductivity-type source region, a second conductivity-type channel region, and a first conductivity-type drain region formed in the semiconductor layer, a second trench selectively formed in a source portion defined in a manner containing the source region in the surface of the semiconductor layer, a trench buried portion buried in the second trench, a second conductivity-type channel contact region selectively disposed at a position higher than that of a bottom portion of the second trench in the source portion, and electrically connected with the channel region, and a surface metal layer disposed on the source portion, and electrically connected to the source region and the channel contact region.

An impurity of a second conductivity type is selectively doped in a surface of a semiconductor substrate of a first conductivity type to form doped regions. A portion of a surface of the doped regions is covered by a heat insulating film. At least a remaining portion of the surface of the doped regions is covered by an absorbing film and the doped regions are heated through the absorbing film, enabling an impurity region of the second conductivity type to be formed having two or more of the doped regions that have a same impurity concentration and differing carrier concentrations.

A semiconductor device of an embodiment includes a layered substance formed by laminating two-dimensional substances in two or more layers. The layered substance includes at least either one of a p-type region having a first intercalation substance between layers of the layered substance and an n-type region having a second intercalation substance between layers of the layered substance. The layered substance includes a conductive region that is adjacent to at least either one of the p-type region and the n-type region. The conductive region includes neither the first intercalation substance nor the second intercalation substance. A sealing member is formed on the conductive region, or on the conductive region and an end of the layered substance.

The present disclosure provides a thin film transistor, a method for producing the same, an array substrate and a display apparatus. An electrode of the thin film transistor is made of Cu or Cu alloy, and an anti-oxidization layer is used to prevent oxidization of Cu. The thin film transistor includes a gate electrode, a gate insulation layer, a semiconductor active layer, a source electrode and a drain electrode provided on a base substrate, wherein the gate electrode and/or the drain and source electrodes is/are made of Cu or Cu alloy. The thin film transistor further includes an anti-oxidization layer made of a topological insulator material, the anti-oxidization layer being provided above and in contact with the gate electrode and/or the source and drain electrodes made of Cu or Cu alloy.

A method for fabricating a nanowire transistor includes the steps of first forming a nanowire channel structure on a substrate, in which the nanowire channel structure includes first semiconductor layers and second semiconductor layers alternately disposed over one another. Next, a gate structure is formed on the nanowire channel structure and then a source/drain structure is formed adjacent to the gate structure, in which the source/drain structure is made of graphene.

A method of patterning a 2D material layer is includes selectively forming a first material layer on a surface of a substrate to form a first region in which the first material layer covers the surface of the substrate and to further form a second region in which the surface of the substrate is exposed from the first material layer, the first material layer having a strong adhesive force with a 2D material. The method further includes forming a 2D material layer is formed in both the first region and the second region. The method further includes selectively removing the 2D material layer from the second region based on using a physical removal method, such that the 2D material layer remains in the first region.

A transistor comprising a channel region on a material is disclosed. The channel region comprises a two-dimensional material comprising opposing sidewalls and oriented perpendicular to the material. A gate dielectric is on the two-dimensional material and gates are on the gate dielectric. Semiconductor devices and systems including at least one transistor are disclosed, as well as methods of forming a semiconductor device.

A stack includes a base portion consisting of silicon carbide and having a first surface that is a Si face and a carbon atom thin film disposed on the first surface and including a first main surface facing the first surface and a second main surface that is a main surface on an opposite side from the first main surface. The carbon atom thin film consists of carbon atoms. The carbon atom thin film includes at least one of a buffer layer that is a carbon atom layer including carbon atoms bonded to silicon atoms forming the Si face and a graphene layer. The second main surface includes a plurality of terraces parallel to the Si face of the silicon carbide forming the base portion and a plurality of steps connecting together the plurality of terraces.