A method for fabricating semiconductor devices, may include forming a dielectric having a central portion with top and bottom surfaces thereof. A first sacrificial material and a second sacrificial material may be formed on the top and bottom surfaces, respectively, of the dielectric. End portions of the dielectric may be replaced with a first source/drain (S/D) metal and a second S/D metal. The central portion of the dielectric may be exposed at least by removing the first sacrificial material and second sacrificial material. Two-dimensional (2D) material may be selectively grown around the central portion of the dielectric

A semiconductor device of the present invention includes a gate electrode buried in a gate trench of a first conductivity-type semiconductor layer, a first conductivity-type source region, a second conductivity-type channel region, and a first conductivity-type drain region formed in the semiconductor layer, a second trench selectively formed in a source portion defined in a manner containing the source region in the surface of the semiconductor layer, a trench buried portion buried in the second trench, a second conductivity-type channel contact region selectively disposed at a position higher than that of a bottom portion of the second trench in the source portion, and electrically connected with the channel region, and a surface metal layer disposed on the source portion, and electrically connected to the source region and the channel contact region.

Methods for the manufacture of semiconductor devices constructed advanced three-dimensional (3D) device architectures using nanosheets with two-dimensional (2D) materials are disclosed. Aspects can include forming a dielectric layer; forming a conductive oxide layer on the dielectric layer; selectively forming a two-dimensional (2D) material around the conductive oxide layer; forming an active gate around the 2D material; and forming a first metal structure and a second metal structure, wherein the dielectric layer and conductive oxide layer extend between the first metal structure and the second metal structure.

A thin-film transistor and a manufacturing method thereof are provided, and the manufacturing method includes: forming a source electrode, a drain electrode and a planarization layer on a substrate, and patterning the planarization layer to form a first portion disposed between the source electrode and the drain electrode, a second portion disposed at a side of the source drain, and a third portion disposed at a side of the drain electrode. Upper surfaces of all the first portion, the second portion, and the third surface are flush with top portions of both the source electrode and the drain electrode.

A semiconductor device has a substrate and graphene with semiconducting properties or diamond region formed on the substrate. The graphene with semiconducting properties or diamond region is formed on or within the substrate using liquid-phase-epitaxy growth of graphene enabled by a catalytic alloy of Ni and Cu. The substrate can be silicon, silicon carbide, gallium arsenide, gallium nitride, germanium, or indium phosphide. A semiconductor component is formed over the graphene with semiconducting properties or diamond region and substrate. The semiconductor component can be a power MOSFET, IGBT, or CTIGBT with a gate structure formed over the substrate, source region adjacent to the gate structure, and drain region adjacent to the gate structure opposite the source region. The graphene with semiconducting properties or diamond region is formed under a gate of the MOSFET to reduce drain to source resistance, as well as providing radiation hardening for the device.

A method for fabricating a nanowire transistor includes the steps of first forming a nanowire channel structure on a substrate, in which the nanowire channel structure includes first semiconductor layers and second semiconductor layers alternately disposed over one another. Next, a gate structure is formed on the nanowire channel structure and then a source/drain structure is formed adjacent to the gate structure, in which the source/drain structure is made of graphene.

An array substrate, a method for forming an array substrate, and a display device are provided. The array substrate includes a substrate, and a gate layer, an active layer, and a source/drain layer formed over the substrate. An insulating layer is formed between the gate layer and the active layer, and the source/drain layer, and the active layer comprises at least one graphene layer and at least one molybdenum disulfide layer disposed in a stack, and the at least one graphene layer is located at a side away from the substrate of the active layer and contacts the source/drain layer.

A semiconductor device and method of manufacturing using carbon nanotubes are provided. In embodiments a stack of nanotubes are formed and then a non-destructive removal process is utilized to reduced the thickness of the stack of nanotubes. A device such as a transistor may then be formed from the reduced stack of nanotubes.

Example embodiments relate to a graphene device, methods of manufacturing and operating the same, and an electronic apparatus including the graphene device. The graphene device is a multifunctional device. The graphene device may include a graphene layer and a functional material layer. The graphene device may have a function of at least one of a memory device, a piezoelectric device, and an optoelectronic device within the structure of a switching device/electronic device. The functional material layer may include at least one of a resistance change material, a phase change material, a ferroelectric material, a multiferroic material, multistable molecules, a piezoelectric material, a light emission material, and a photoactive material.

In some embodiments, a semiconductor structure can include: a diamond substrate having a surface conductive layer; a heavily doped region formed in the diamond substrate; and a metal contact positioned over the conductive surface layer such that a first portion of the heavily doped region is covered by the metal contact and a second portion of the heavily doped region is not covered by the metal contact.