H01L29/66045

Metal oxide semiconductor field effect transistor and method of manufacturing same
11222959 · 2022-01-11 · ·

A Field Effect Transistor (FET) device and a method for manufacturing it are disclosed. The FET device contains a graphene layer, a composite gate dielectric layer disposed above the graphene layer, wherein the composite gate layer is passivated with fluorine, and a metal gate disposed above the composite gate dielectric layer. The method disclosed teaches how to manufacture the FET device.

Semiconductor device and method for manufacturing the same
11217674 · 2022-01-04 · ·

A semiconductor device of the present invention includes a gate electrode buried in a gate trench of a first conductivity-type semiconductor layer, a first conductivity-type source region, a second conductivity-type channel region, and a first conductivity-type drain region formed in the semiconductor layer, a second trench selectively formed in a source portion defined in a manner containing the source region in the surface of the semiconductor layer, a trench buried portion buried in the second trench, a second conductivity-type channel contact region selectively disposed at a position higher than that of a bottom portion of the second trench in the source portion, and electrically connected with the channel region, and a surface metal layer disposed on the source portion, and electrically connected to the source region and the channel contact region.

METHOD OF MANUFACTURING SEMICONDUCTOR ELEMENT

A method may be used for manufacturing a semiconductor element. The method may include the following steps: preparing a substrate; forming a semiconductor layer on the substrate, wherein the semiconductor layer includes crystallized two-dimensional layers; forming a source electrode and a drain electrode on the semiconductor layer; forming an semiconductor member by wet etching the semiconductor layer using sodium hypochlorite as an etchant, wherein the wet etching results in a residue; and removing the residue using purified water and an inert gas.

MASK-BASED DIAGNOSTIC DEVICE AND WAFER-LEVEL FUNCTIONALIZATION OF A PACKAGED SEMICONDUCTOR BIOSENSOR
20230333038 · 2023-10-19 ·

A mask-based diagnostic device, includes a face mask, where an inside of the face mask defines during use a confined local environment that includes breath vapor exhaled from the lungs of a user. An exhaled breath condensate (EBC) collector has a condensate forming surface for converting exhaled breath vapor into an EBC liquid sample. The EBC collector includes a thermal mass cooled before use to a condensation forming temperature less than a confined environment temperature of the confined environment inside of the face mask, and an EBC testing unit for testing the EBC sample for a target molecule, where the EBC sample contains water and the target molecule, the EBC testing unit includes a printed circuit board supporting a semiconductor packaged electronic biosensor in electrical communication with power, analysis and communications electronics, a fluid conductor for conducting the EBC sample to the electronic biosensor.

COMPOSITE OXIDE SEMICONDUCTOR AND METHOD FOR MANUFACTURING THE SAME
20230335598 · 2023-10-19 ·

The field-effect mobility and reliability of a transistor including an oxide semiconductor film are improved. A semiconductor layer of a transistor is formed using a composite oxide semiconductor in which a first region and a second region are mixed. The first region includes a plurality of first clusters containing one or more of indium, zinc, and oxygen as a main component. The second region includes a plurality of second clusters containing one or more of indium, an element M (M represents Al, Ga, Y, or Sn), zinc, and oxygen. The first region includes a portion in which the plurality of first clusters are connected to each other. The second region includes a portion in which the plurality of second clusters are connected to each other.

TRANSISTOR AND METHOD FOR FABRICATING THE SAME

A transistor and a fabrication method thereof are provided. The transistor includes a substrate, a low-dimensional material layer provided above the substrate, a gate, a source, a drain, a gate dielectric layer, and spacers. The source is located at a first side of the gate. The drain is located at a second side of the gate. The gate dielectric layer is provided between the gate and the low-dimensional material layer. The spacers are provided between the source and the gate and between the drain and the gate, respectively, in which dipoles are formed in the spacers to electrostatically dope the low-dimensional material layer. In the transistor, the dipoles in the spacers may be used to electrostatically dope the channel in the spacer region.

Method of manufacturing semiconductor devices including the steps of removing a plurality of spacers that surrounds each of the plurality of nanotubes into a layer of nanotubes, and forming gate dielectric and/or gate electrode

A semiconductor device and method of manufacturing using carbon nanotubes are provided. In embodiments a stack of nanotubes are formed and then a non-destructive removal process is utilized to reduce the thickness of the stack of nanotubes. A device such as a transistor may then be formed from the reduced stack of nanotubes.

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME

A semiconductor device includes a SiC semiconductor layer that has a carbon density of 1.0×10.sup.22 cm.sup.-3 or more, a SiO.sub.2 layer that is formed on the SiC semiconductor layer and that has a connection surface contiguous to the SiC semiconductor layer and a non-connection surface positioned on a side opposite to the connection surface, a carbon-density-decreasing region that is formed at a surface layer portion of the connection surface of the SiO.sub.2 layer and in which a carbon density gradually decreases toward the non-connection surface of the SiO.sub.2 layer, and a low carbon density region that is formed at a surface layer portion of the non-connection surface of the SiO.sub.2 layer and that has a carbon density of 1.0×10.sup.19 cm.sup.-3 or less.

Semiconductor device and method for manufacturing the same
11817487 · 2023-11-14 · ·

A semiconductor device of the present invention includes a gate electrode buried in a gate trench of a first conductivity-type semiconductor layer, a first conductivity-type source region, a second conductivity-type channel region, and a first conductivity-type drain region formed in the semiconductor layer, a second trench selectively formed in a source portion defined in a manner containing the source region in the surface of the semiconductor layer, a trench buried portion buried in the second trench, a second conductivity-type channel contact region selectively disposed at a position higher than that of a bottom portion of the second trench in the source portion, and electrically connected with the channel region, and a surface metal layer disposed on the source portion, and electrically connected to the source region and the channel contact region.

Method of Manufacturing Semiconductor Devices

A semiconductor device and method of manufacturing using carbon nanotubes are provided. In embodiments a stack of nanotubes are formed and then a non-destructive removal process is utilized to reduce the thickness of the stack of nanotubes. A device such as a transistor may then be formed from the reduced stack of nanotubes.