To provide a semiconductor device having excellent conduction characteristics of a transistor portion and a diode portion. The semiconductor device having a transistor portion and a diode portion, the semiconductor device includes: a drift region of a first conductivity type provided on a semiconductor substrate, a first well region of a second conductivity type provided on an upper surface side of the semiconductor substrate, an anode region of the second conductivity provided on the upper surface side of the semiconductor substrate, in the diode portion, and a first high concentration region of a second conductivity type which is provided in contact with a first well region between the anode region and the first well region, and has a higher doping concentration than the anode region.

A diode pack comprises a plurality of diodes seated in an assembly within a housing. The diode pack also includes a plurality of radial studs extending from an axial end of the housing relative to an axis of rotation extending through the housing. Each of the radial studs is electrically connected to a respective diode within the assembly. The diode pack further includes a center stud captured within the housing between the assembly and the housing and along the axis of rotation. A method of making a diode pack includes forming a housing of an electrically insulate material, removing a portion of the housing along an axis of rotation of the housing, mounting a center stud in the housing where the portion was removed, and assembling an assembly of diodes into the housing.

A number of diode limiter semiconductor structures are described. The diode limiters can include a hybrid arrangement of diodes with different intrinsic regions, all formed over the same semiconductor substrate. In one example, a diode limiter includes a first diode having a first doped region formed to a first depth into an intrinsic layer of a semiconductor structure, a second diode having a second doped region formed to a second depth into the intrinsic layer of the semiconductor structure, and at least one passive component. The first diode includes a first effective intrinsic region of a first thickness, the second diode includes a second effective intrinsic region of a second thickness. The first thickness is greater than the second thickness. The passive component is over the intrinsic layer and electrically coupled as part of the diode limiter.

To suppress an increase in RC-IGBT recovery loss. In a semiconductor device, an IGBT region includes a base layer of a second conductivity type in a surface layer of a drift layer, a diode region includes an anode layer of a second conductivity type in the surface layer of the drift layer, a termination region includes a well layer of the second conductivity type in the surface layer of the drift layer, an impurity concentration profile of the base layer and an impurity concentration profile of the anode layer in a direction along an upper surface of the drift layer cyclically fluctuate, and the impurity concentration profile of the base layer and the impurity concentration profile of the anode layer are different.

A method for manufacturing a three-dimensional semiconductor diode device comprises providing a substrate comprising a silicon substrate and a first oxide layer formed on the silicon substrate; depositing a plurality of stacked structures on the substrate, each of the stacked structures comprising a dielectric layer and a conductive layer; etching the stacked structures through a photoresist layer which is patterned to form at least one trench in the stacked structures, a bottom of the trench exposing the first oxide layer; depositing a second oxide layer on the stacked structures and the trench; depositing a high-resistance layer on the second oxide layer, the high-resistance layer comprising a first polycrystalline silicon layer and a first conductive compound layer; and depositing a low-resistance layer on the high-resistance layer, the low-resistance layer comprising a second polycrystalline silicon layer and a second conductive compound layer.

According to various embodiments, there is provided a diode device including a semiconductor substrate of a first conductivity type, a first semiconductor region formed within the semiconductor substrate, an epitaxial region of the first conductivity type, and a second semiconductor region of a second conductivity type different from the first conductivity type. The first semiconductor region includes a chalcogen. The epitaxial region is formed over the first semiconductor region. The second semiconductor region is formed over the epitaxial region.

Systems and methods for transferring logging data from an offset well location to a target well location by adjusting the logging data to account for the difference in correlated depths between the target well and the offset well where logging data is acquired.

A power diode includes a semiconductor body having an anode region and a drift region, the semiconductor body being coupled to an anode metallization of the power diode and to a cathode metallization of the power diode, and an anode contact zone and an anode damage zone, both implemented in the anode region, the anode contact zone being arranged in contact with the anode metallization, and the anode damage zone being arranged in contact with and below the anode contact zone, wherein fluorine is included within each of the anode contact zone and the anode damage zone at a fluorine concentration of at least 1016 atoms*cm-3.

A single chip power diode includes a semiconductor body having an anode region coupled to a first load terminal and a cathode region coupled to a second load terminal. An edge termination region surrounding an active region is terminated by a chip edge. The semiconductor body thickness is defined by a distance between at least one first interface area formed between the first load terminal and the anode region and a second interface area formed between the second load terminal and the cathode region. At least one inactive subregion is included in the active region. Each inactive subregion: has a blocking area with a minimal lateral extension of at least 20% of a drift region thickness; configured to prevent crossing of the load current between the first load terminal and the semiconductor body through the blocking area; and at least partially not arranged adjacent to the edge termination region.

A transient voltage suppression device includes a substrate; a first conductivity type well region disposed in the substrate and comprising a first well and a second well; a third well disposed on the substrate, a bottom part of the third well extending to the substrate; a fourth well disposed in the first well; a first doped region disposed in the second well; a second doped region disposed in the third well; a third doped region disposed in the fourth well; a fourth doped region disposed in the fourth well; a fifth doped region extending from inside of the fourth well to the outside of the fourth well, a portion located outside the fourth well being located in the first well; a sixth doped region disposed in the first well; a seventh doped region disposed below the fifth doped region and in the first well.