A high-performance HBT that is unlikely to decrease the process controllability and to increase the manufacturing cost is implemented. A heterojunction bipolar transistor includes an emitter layer, a base layer, and a collector layer on a GaAs substrate. The emitter layer is formed of InGaP. The base layer is formed of GaAsPBi having a composition that substantially lattice-matches GaAs.

Methods and devices are provided herein for enhancing robustness of a bipolar electrostatic discharge (ESD) device. The robustness of a bipolar ESD device includes providing an emitter region and a collector region adjacent to the emitter region. An isolation structure is provided between the emitter region and the collector region. A ballasting characteristic at the isolation structure is modified by inserting at least one partition structure therein. Each partition structure extends substantially abreast at least one of the emitter and the collector regions.

A process for fabricating a vertical transistor is provided, including steps of providing a substrate surmounted by a stack of first to third layers made of first to third semiconductors materials of two different types; partially etching the first and third layers with an etching that is selective, so as to form a first void in the first layer and a third void in the third layer, extending to the lower surface and to the upper surface of the second layer, respectively; filling the voids in order to form spacers making contact with the lower surface and the upper surface, respectively; partially etching the second layer with an etching that is selective, so as to form a second void between the first and second spacers; and depositing a conductor material in the second void.

A mesa structure including a collector layer, a base layer, and an emitter layer laminated on a substrate is formed. An emitter electrode electrically connected to the emitter layer is disposed on the mesa structure. Moreover, a base electrode electrically connected to the base layer is disposed on the mesa structure. A collector electrode is disposed in such a manner as to surround the mesa structure in plan view, and the collector electrode is electrically connected to the collector layer. The emitter electrode includes a first part and a second part. In plan view, the base electrode surrounds the first part of the emitter electrode, and the second part of the emitter electrode surrounds the base electrode.

The present disclosure provides a semiconductor structure and a manufacturing method thereof. In the manufacturing method, a first P-type semiconductor layer is provided, and an N-type semiconductor layer and a second P-type semiconductor layer are formed in sequence on the first P-type semiconductor layer. The first P-type semiconductor layer, the N-type semiconductor layer and the second P-type semiconductor layer all include a GaN-based material. When the first P-type semiconductor layer is provided, its upper surface is controlled to be a Ga surface; when the N-type semiconductor layer is formed, its upper surface is controlled to be an N surface; when the second P-type semiconductor layer is formed, its upper surface is controlled to be an N surface.

Embodiments include a first set of fins having an emitter of a bipolar junction transistor (BJT) disposed over the first set of fins, a second set of fins having a base of the BJT disposed over the second set of fins, and a third set of fins having a collector of the BJT disposed over the third set of fins. A first gate structure is disposed over the first set of fins adjacent to the emitter. A second gate structure is disposed over the second set of fins adjacent to the base. A third gate structure is disposed over the third set of fins adjacent to the collector. The first gate structure, second gate structure, and third gate structure are physically and electrically separated.

A method for forming a bipolar junction transistor includes forming a collector intrinsic region, an emitter intrinsic region and an intrinsic base region between the collector intrinsic region and the emitter intrinsic region. A collector extrinsic contact region is formed in direct contact with the collector intrinsic region; an emitter extrinsic contact region is formed on the emitter intrinsic region and a base extrinsic contact region is formed in direct contact with the intrinsic base region. Carbon is introduced into at least one of the collector extrinsic contact region, the emitter extrinsic contact region and the base extrinsic contact region to suppress diffusion of dopants into the junction region.

A method of manufacturing a structure in a semiconductor body comprises forming a first mask above a first surface of the semiconductor body. The first mask comprises an opening surrounding a first portion of the first mask, thereby separating the first portion and a second portion of the first mask. The semiconductor body is processed through the opening at the first surface. The opening is increased by removing at least part of the first mask in the first portion while maintaining the first mask in the second portion. The semiconductor body is further processed through the opening at the first surface.

A semiconductor device that includes a bipolar transistor, wherein a third opening, through which a pillar bump and a second wiring line, which is electrically connected to an emitter layer, contact each other, is shifted in a longitudinal direction of the emitter layer away from a position at which the third opening would be directly above the emitter layer. The third opening is arranged, with respect to the emitter layer, such that an end portion of the emitter layer in the longitudinal direction of the emitter layer and the edge of the opening of the third opening are substantially aligned with each other.

A method includes forming a first polysilicon structure over a first portion of a substrate. A second polysilicon structure is formed over a second portion of the substrate. Two spacers are formed on opposite sidewalls of the second polysilicon structure. A layer of protective material is formed to cover the first and second portions of the substrate. The layer of protective material has a first thickness over the second polysilicon structure and a second thickness over the two spacers. The first thickness is equal to or greater than 500 ?, and the second thickness is equal to or less than 110% of the first thickness. A patterned photo resist layer is formed to cover a first portion of the layer of protective material that covers the first portion of the substrate. The second portion of the layer of protective material is removed.