A bipolar transistor includes a collector. The collector is produced by a process wherein a first substantially homogeneously doped layer is formed at the bottom of a cavity. A second gradually doped layer is then formed by diffusion of dopants of the first substantially homogeneously doped layer.

A method for producing a semiconductor device, the method includes, forming, on a substrate made from a semiconductor substance, at least one bipolar junction (BJ) transistor including a first terminal connected to a first well, the first well formed in the substrate and includes a first dopant having a first dopant concentration. At least one non-BJ transistor is formed on the substrate, the non-BJ transistor includes a second terminal connected to a second well, and the second well formed in the substrate and includes a second dopant having a same polarity as the first dopant. The first dopant concentration of the BJ transistor is higher than the second dopant concentration of the non-BJ transistor.

A power amplifier comprising amplifier circuits of multiple stages. Each of the amplifier circuits of multiple stages includes a bipolar transistor and a base electrode. The bipolar transistor included in each of the amplifier circuits of multiple stages includes a collector layer, a base layer placed on the collector layer, and an emitter mesa placed on part of the region of the base layer. The emitter mesa has a shape elongated in one direction in plan view. The base electrode includes a base main portion arranged in such a manner as to be separated from the emitter mesa with a gap in a direction orthogonal to a lengthwise direction of the emitter mesa in plan view. The base main portion has a shape elongated in a direction parallel to the lengthwise direction of the emitter mesa in plan view and is electrically connected to the base layer.

A method includes implanting dopant of a first conductivity type into an epitaxial layer of semiconductor material to form first and second false collector regions adjacent to the surface of the epitaxial layer. The first false collector region is located laterally on a first side of a base region. The base region is formed within the epitaxial layer from dopant of a second conductivity type that is opposite the first conductivity type. The second false collector region is located laterally on a second side of the base region. The second side is opposite the first side of the base region. The base region is a base of a parasitic bipolar junction in an isolation region of an active semiconductor device.

The present application teaches, among other innovations, power semiconductor devices in which breakdown initiation regions, on BOTH sides of a die, are located inside the emitter/collector regions, but laterally spaced away from insulated trenches which surround the emitter/collector regions. Preferably this is part of a symmetrically-bidirectional power device of the “B-TRAN” type. In one advantageous group of embodiments (but not all), the breakdown initiation regions are defined by dopant introduction through the bottom of trench portions which lie within the emitter/collector region. In one group of embodiments (but not all), these can advantageously be separated trench portions which are not continuous with the trench(es) surrounding the emitter/collector region(s).

Embodiments of the disclosure provide a bipolar transistor structure having a base with a varying horizontal width and methods to form the same. The bipolar transistor structure includes a first emitter/collector (E/C) layer on an insulator layer. A base layer is over the insulator layer. A spacer between the first E/C layer and the base layer. The base layer includes a lower base region, and the spacer is adjacent to the lower base region and the first E/C layer. An upper base region is on the lower base region and the spacer. A horizontal width of the upper base region is larger than a horizontal width of the lower base region.

An integrated circuit includes a first base that has at least a part formed of a first semiconductor material and that includes an electric circuit, a second base that has at least a part formed of a second semiconductor material having a thermal conductivity lower than the first semiconductor material and that includes a power amplifier circuit, and a high thermal conductive member that has at least a part formed of a high thermal conductive material having a thermal conductivity higher than the first semiconductor material and that is disposed between the electric circuit and the power amplifier circuit. At least a part of the high thermal conductive member overlaps at least a part of the first base and at least a part of the second base in plan view. The high thermal conductive member is in contact with the first base and the second base.

Methods and devices are provided herein for enhancing robustness of a bipolar electrostatic discharge (ESD) device. The robustness of a bipolar ESD device includes providing an emitter region and a collector region adjacent to the emitter region. An isolation structure is provided between the emitter region and the collector region. A ballasting characteristic at the isolation structure is modified by inserting at least one partition structure therein. Each partition structure extends substantially abreast at least one of the emitter and the collector regions.

A device including a transistor is fabricated by forming a first part of a first region of the transistor through the implantation of dopants through a first opening. The second region of the transistor is then formed in the first opening by epitaxy.

An integrated circuit includes an N-type laterally diffused metal-oxide semiconductor (NLDMOS) transistor including an active semiconductor substrate region having P-type conductivity. The integrated circuit further includes a buried semiconductor region having N+-type conductivity underneath the active substrate region. The buried semiconductor region is more heavily doped than the active semiconductor substrate region.