The present disclosure relates to semiconductor structures and, more particularly, to vertical bipolar transistors and methods of manufacture. The structure includes: an intrinsic base region comprising semiconductor-on-insulator material; a collector region confined within an insulator layer beneath the semiconductor-on-insulator material; an emitter region above the intrinsic base region; and an extrinsic base region above the intrinsic base region.

A semiconductor device includes a substrate, a first polysilicon structure over a first portion of the substrate, and a first spacer on a sidewall of the first polysilicon structure. The first spacer has a concave corner region between an upper portion and a lower portion. The semiconductor device includes a second polysilicon structure over a second portion of the substrate. The semiconductor device includes a second spacer on a sidewall of the second polysilicon structure. The semiconductor device further includes a protective layer covering an entirety of the first spacer and the first polysilicon structure, wherein the protective layer has a first thickness over the concave corner region and a second thickness over the first polysilicon structure, a difference between the first thickness and the second thickness is at most 10% of the second thickness, and the protective layer exposes a top-most portion of a sidewall of the second spacer.

In one embodiment, a TVS semiconductor device includes a P-N diode that is connected in parallel with a bipolar transistor wherein a breakdown voltage of the bipolar transistor is less than a breakdown voltage of the P-N diode.

An electronic device includes a substrate having a second conductivity type including a semiconductor surface layer with a buried layer (BL) having a first conductivity type. In the semiconductor surface layer is a first doped region (e.g., collector) and a second doped region (e.g., emitter) both having the first conductivity type, with a third doped region (e.g., a base) having the second conductivity type within the second doped region, wherein the first doped region extends below and lateral to the third doped region. At least one row of deep trench (DT) isolation islands are within the first doped region each including a dielectric liner extending along a trench sidewall from the semiconductor surface layer to the BL with an associated deep doped region extending from the semiconductor surface layer to the BL. The deep doped regions can merge forming a merged deep doped region that spans the DT islands.

A bipolar junction transistor (BJT) containing sensor that includes a vertically oriented stack of an emitter overlying a supporting substrate, a base region present directly atop the emitter and a collector atop the base region. A first extrinsic base region is in contact with a first sidewall of a vertically oriented base region. The first extrinsic base region is electrically contacted to provide the bias current of the bipolar junction transistor during sensor operation. A second extrinsic base region is in contact with a second sidewall of the base region. The second extrinsic base region includes a sensing element. A sample trench is present adjacent to the BJT having a trench sidewall provided by the sensing element.

Methods and devices are provided herein for enhancing robustness of a bipolar electrostatic discharge (ESD) device. The robustness of a bipolar ESD device includes providing an emitter region and a collector region adjacent to the emitter region. An isolation structure is provided between the emitter region and the collector region. A ballasting characteristic at the isolation structure is modified by inserting at least one partition structure therein. Each partition structure extends substantially abreast at least one of the emitter and the collector regions.

Disclosed examples provide fabrications methods and integrated circuits with back ballasted NPN bipolar transistors which include an n-type emitter in a P doped region, a p-type base with a first side facing the emitter, and an n-type collector laterally spaced from a second side of the base, where the collector includes a first side facing the second side of the base, an opposite second side, a silicided first collector portion and a silicide blocked second collector portion covered with a non-conductive dielectric that extends laterally between the first collector portion and the second side of the collector to provide back side ballasting for lateral breakdown and low current conduction via a deep N doped region while the vertical NPN turns on at a high voltage.

A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate, a first well, a second well and doped regions. The substrate has heavily doped and lightly doped regions over the heavily doped region. The first wells are disposed in the lightly doped region and arranged as an array. The first wells have a conductive type opposite to a conductive type of the heavily doped and lightly doped regions. The second well is disposed in the substrate over the lightly doped region, and has an active region defined by an isolation structure. The first wells are overlapped with the second well. Top ends of the first wells are lower than a bottom end of the second well. The doped regions are separately located in the active region, and have a conductive type opposite to a conductive type of the second well.

An electronic device includes a substrate having a second conductivity type including a semiconductor surface layer with a buried layer (BL) having a first conductivity type. In the semiconductor surface layer is a first doped region (e.g., collector) and a second doped region (e.g., emitter) both having the first conductivity type, with a third doped region (e.g., a base) having the second conductivity type within the second doped region, wherein the first doped region extends below and lateral to the third doped region. At least one row of deep trench (DT) isolation islands are within the first doped region each including a dielectric liner extending along a trench sidewall from the semiconductor surface layer to the BL with an associated deep doped region extending from the semiconductor surface layer to the BL. The deep doped regions can merge forming a merged deep doped region that spans the DT islands.

A method includes forming a base layer on a top surface of a substrate. A dielectric layer is formed on exposed surfaces of the base layer. A hardmask layer is formed on the base layer and the dielectric layer. A pattern is formed from the hardmask with a first opening and a second opening. Portions of a dielectric layer are removed from the top surface of the base layer at positions consistent with the pattern of the first opening and the second opening to form exposed surfaces defined as a first window and a second window in the dielectric layer. Deposits of a dopant-containing layer are limited on the exposed surfaces of: a first portion on the top surface of the base layer inside of the first window, and a second portion on the top surface of the base layer inside of the second window.