A method of processing a semiconductor device includes: creating first and second recesses in a surface of a semiconductor body; creating an insulation layer that forms first and second wells each having a common lateral extension range with the portion of the insulation layer located between the recesses; filling the wells with a plug material having the respective common lateral extension range with the insulation layer; removing a middle portion of the insulation layer located between the recesses; filling, with a filling material, a third recess created in a region where the middle portion has been removed and at least a portion of the space located between the wells; creating a first common surface of the insulation layer, the plug material, and the filling material; removing the plug material from the second well; and creating a second insulation layer that covers a side wall of the second recess.

A cell includes a Z.sup.2-FET-type structure that is formed with two front gates extending over an intermediate region between an anode region and a cathode region. The individual front gates of the two front gates are spaced apart by a distance that is shorter than 40% of a width of each individual front gate.

A semiconductor arrangement and methods of formation are provided. A semiconductor arrangement includes a semiconductor column on a buffer layer over a substrate. The buffer layer comprises a conductive material. Both a first end of the semiconductor column and a bottom contact are connected to a buffer layer such that the first end of the semiconductor column and the bottom contact are connected to one another through the buffer layer, which reduces a contact resistance between the semiconductor column and the bottom contact. A second end of the semiconductor column is connected to a top contact. In some embodiments, the first end of the semiconductor column corresponds to a source or drain of a transistor and the second end corresponds to the drain or source of the transistor.

Tunnel field effect transistors include a semiconductor substrate; a source region in the semiconductor substrate; a drain region in the semiconductor substrate; a channel region in the semiconductor substrate between the source region and the drain region; and a gate electrode on the semiconductor substrate above the channel region. The source region comprises a first region having a first conductivity type, a third region having a second conductivity type that is different from the first conductivity type, and a second region having an intrinsic conductivity type that is between the first region and the third region.

In one embodiment, a breakdown voltage blocking device can include an epitaxial region located above a substrate and a plurality of source trenches formed in the epitaxial region. Each source trench can include a dielectric layer surrounding a conductive region. The breakdown voltage blocking device can also include a contact region located in an upper surface of the epitaxial region along with a gate trench formed in the epitaxial region. The gate trench can include a dielectric layer that lines the sidewalls and bottom of the gate trench and a conductive region located between the dielectric layer. The breakdown voltage blocking device can include source metal located above the plurality of source trenches and the contact region. The breakdown voltage blocking device can include gate metal located above the gate trench.

A semiconductor device includes a semiconductor substrate, at least a first field-effect structure integrated in the semiconductor substrate and at least a second field-effect structure integrated in the semiconductor substrate. The first field-effect structure includes a first gate electrode comprised of a polycrystalline semiconductor material. The second field-effect structure includes a second gate electrode comprised of one of a metal, a metal alloy, a metal layer stack, a metal alloy layer stack and any combination thereof.

A method and structure for suppressing band-to-band tunneling current in a semiconductor device having a high-mobility channel material includes forming a channel region adjacent to and in contact with one of a source region and a drain region. A tunnel barrier layer may be formed such that the tunnel barrier layer is interposed between, and in contact with, the channel region and one of the source region and the drain region. In some embodiments, a gate stack is then formed over at least the channel region. In various examples, the tunnel barrier layer includes a first material, and the channel region includes a second material different than the first material. In some embodiments, the semiconductor device may be oriented in one of a horizontal or vertical direction, and the semiconductor device may include one of a single-gate or multi-gate device.

Epitaxial oxide plugs are described for imposing strain on a channel region of a proximate channel region of a transistor. The oxide plugs form epitaxial and coherent contact with one or more source and drain regions adjacent to the strained channel region. The epitaxial oxide plugs can be used to either impart strain to an otherwise unstrained channel region (e.g., for a semiconductor body that is unstrained relative to an underlying buffer layer), or to restore, maintain, or increase strain within a channel region of a previously strained semiconductor body. The epitaxial crystalline oxide plugs have a perovskite crystal structure in some embodiments.

A Tunnel Field-Effect Transistor (TFET) includes a source region in a semiconductor substrate, and a drain region in the semiconductor substrate. The source region and the drain region are of opposite conductivity types. The TFET further includes a gate stack over the semiconductor substrate, with the source region and the drain region extending to opposite sides of the gate stack. The gate stack includes a gate dielectric over the semiconductor substrate, and a ferroelectric layer over the gate dielectric.

The present invention concerns a semiconductor tunneling Field-Effect device including a source, a drain, at least one elongated semiconductor structure extending in an elongated direction, a first gate, and a second gate. The first gate has a length extending in said elongated direction and is positioned on a first side of the at least one elongated semiconductor structure, and the second gate has a length extending in said elongated direction and is positioned on a second opposing side of the at least one elongated semiconductor structure. The first and second gates extend along the first and second sides of the at least one elongated semiconductor structure to define an overlap zone sandwiched between the first gate and the second gate, said overlap zone extending the full length of the first and/or second gate along the at least one elongated semiconductor structure.