Structures for a silicon-controlled rectifier and methods of forming a structure for a silicon-controlled rectifier. The structure includes first and second wells in the semiconductor substrate, a first terminal including a first doped region in the first well, and a second terminal including a second doped region in the second well. The first well and the second doped region have a first conductivity type, and the second well and the first doped region have a second conductivity type opposite to the first conductivity type. First and second conductor layers are positioned on the semiconductor substrate. The first conductor layer partially overlaps with the first well, and the second conductor layer partially overlaps with the second well. A third doped region, which has the second conductivity type, is laterally positioned in the semiconductor substrate between the first and second conductor layers.

After the various regions of a vertical power device are formed in or on the top surface of an n-type wafer, the wafer is thinned, such as by grinding. A drift layer may be n-type, and various n-type regions and p-type regions in the top surface contact a top metal electrode. A blanket dopant implant through the bottom surface of the thinned wafer is performed to form an n− buffer layer and a bottom p+ emitter layer. Energetic particles are injected through the bottom surface to intentionally damage the crystalline structure. A wet etch is performed, which etches the damaged crystal at a much greater rate, so some areas of the n− buffer layer are exposed. The bottom surface is metallized. The areas where the metal contacts the n− buffer layer form cathodes of an anti-parallel diode for conducting reverse voltages, such as voltage spikes from inductive loads.

A semiconductor memory device may include a first electrode and a second electrode, which are spaced apart from each other in a first direction, and a first semiconductor pattern, which is in contact with both of the first and second electrodes. The first semiconductor pattern may include first to fourth sub-semiconductor patterns, which are sequentially disposed in the first direction. The first and fourth sub-semiconductor patterns may be in contact with the first and second electrodes, respectively. The first and third sub-semiconductor patterns may be of a first conductivity type, and the second and fourth sub-semiconductor patterns may be of a second conductivity type different from the first conductivity type. Each of the first to fourth sub-semiconductor patterns may include a transition metal and a chalcogen element.

An integrated gate-commutated thyristor (IGCT) includes a semiconductor wafer having a first main side and a second main side opposite to the first main side and a plurality of first type thyristor cells and second type thyristor cells. The cathode electrode of the first type thyristor cells forms an ohmic contact with the cathode region and the cathode electrode of the second type thyristor cells is insulated from the cathode region. A predefined percentage of second type thyristor cells of the overall amount of first type thyristor cells and second type thyristor cells in a segment ring is greater than 0% and less than or equal to 75%.

A method for fabricating a vertical memory device includes: forming a memory cell array that includes a vertical thyristor and a word line over a first substrate; forming a peripheral circuit unit in a second substrate; bonding the memory cell array with the peripheral circuit unit; removing the first substrate to expose one side of the vertical thyristor; and forming a bit line that is coupled to the one side of the vertical thyristor and the peripheral circuit unit.

Thyristor semiconductor device comprising an anode region, a first base region and a second base region having opposite types of conductivity, and a cathode region, all superimposed along a vertical axis.

An insulated gate turn-off (IGTO) device, formed as a die, has a layered structure including a p+ layer (e.g., a substrate), an n− epi layer, a p-well, trenched insulated gate regions formed in the p-well, and n+ regions between the gate regions, so that vertical NPN and PNP transistors are formed. The device may be formed of a matrix of cells or may be interdigitated. To turn the device on, a positive voltage is applied to the gate, referenced to the cathode. The cells further contain a vertical p-channel MOSFET, for rapidly turning the device off. The p-channel MOSFET may be made a depletion mode device by implanting boron ions at an angle into the trenches to create a p-channel. This allows the IGTO device to be turned off with a zero gate voltage while in a latch-up condition, when the device is acting like a thyristor.

A semiconductor memory device according to the present inventive concept includes: a semiconductor substrate; a common source semiconductor layer doped with impurities of a first conductivity type on the semiconductor substrate; a plurality of insulating layers and a plurality of word line structures alternately stacked on the common source semiconductor layer; and a memory cell dielectric layer penetrating the plurality of insulating layers and the plurality of word line structures and covering an internal wall of a channel hole extending in a vertical direction, and a memory cell structure filling the channel hole. The memory cell structure includes a channel layer, which has the memory cell dielectric layer thereon and fills at least a portion of the channel hole, and a drain layer covering an upper surface of the channel layer, doped with impurities of a second conductivity type, and filling some of an upper portion of the channel hole.

A high power vertical insulated-gate switch is described that includes a parallel cell array having inner cells and an edge cell. The cells have a vertical npnp structure with a trenched field effect device that turns the device on and off. The edge cell is prone to breaking down at high currents. Techniques used to cause the current in the edge cell to be lower than the current in the inner cells, to improve robustness, include: forming a top n-type source region to not extend completely across opposing trenches in areas of the edge cell; forming the edge cell to have a threshold voltage of its field effect device that is greater than the threshold voltage of the field effect devices in the inner cells; and providing a resistive layer between the edge cell and a top cathode electrode electrically contacting the inner cells and the edge cell.

A method of writing data into a volatile thyristor memory cell array and maintaining the data with refresh is disclosed.