Provided is a HEMT device, including: a substrate, an epitaxial layer, a source, a drain, a gate, a conductive layer, an electrocoupling structure, and a high-resistance structure. The epitaxial layer is disposed on the substrate, and includes: a first semiconductor stack layer and a second semiconductor layer disposed on the first semiconductor stack layer; wherein a two-dimensional electron gas is formed at an interface between the first semiconductor stack layer and the second semiconductor layer. The conductive layer is disposed within the epitaxial layer and between the substrate and the two-dimensional electron gas. An end of the electrocoupling structure is electrically connected to the gate, and the other end extends into the epitaxial layer and is electrically connected to the conductive layer. The high-resistance structure is at least partially disposed between the conductive layer and the two-dimensional electron gas, and between the electrocoupling structure and the two-dimensional electron gas.

Some embodiments of the present disclosure provide a semiconductor device. The semiconductor device includes a semiconductive substrate. A donor-supply layer is over the semiconductive substrate. The donor-supply layer includes a top surface. A gate structure, a drain, and a source are over the donor-supply layer. A passivation layer covers conformably over the gate structure and the donor-supply layer. A gate electrode is over the gate structure. A field plate is disposed on the passivation layer between the gate electrode and the drain. The field plate includes a bottom edge. The gate electrode having a first edge in proximity to the field plate, the field plate comprising a second edge facing the first edge, a horizontal distance between the first edge and the second edge is in a range of from about 0.05 to about 0.5 micrometers.

The present disclosure relates to semiconductor devices, manufacturing methods, a power amplification circuits, and electronic devices. One example semiconductor device includes a substrate, a channel layer and a barrier layer sequentially disposed on the substrate in a stacked manner, a source, a gate, and a drain disposed on the barrier layer, a backside via through a region from the substrate to the barrier layer below the source, and a backside conductive layer covering the backside via and a back surface of the substrate, where the source is in contact with and connected to the backside conductive layer.

Some embodiments of the present disclosure provide a semiconductor device. The semiconductor device includes a semiconductive substrate. A donor-supply layer is over the semiconductive substrate. The donor-supply layer includes a top surface. A gate structure, a drain, and a source are over the donor-supply layer. A passivation layer covers conformally over the gate structure and the donor-supply layer. A gate electrode is over the gate structure. A field plate is disposed on the passivation layer between the gate electrode and the drain. The field plate includes a bottom edge. The gate electrode having a first edge in proximity to the field plate, the field plate comprising a second edge facing the first edge, a horizontal distance between the first edge and the second edge is in a range of from about 0.05 to about 0.5 micrometers.

An electronic device and associated methods are disclosed. In one example, the electronic device includes an electronic package substrate including a glass core layer and a regulator circuit. A first portion of the circuit components of the regulator circuit is embedded in the glass core layer and a second portion of the circuit components of the regulator circuit is formed on a surface of the glass core layer.

Some embodiments of the present disclosure provide a semiconductor device. The semiconductor device includes a semiconductive substrate. A donor-supply layer is over the semiconductive substrate. The donor-supply layer includes a top surface. A gate structure, a drain, and a source are over the donor-supply layer. A passivation layer covers conformally over the gate structure and the donor-supply layer. A gate electrode is over the gate structure. A field plate is disposed on the passivation layer between the gate electrode and the drain. The field plate includes a bottom edge. The gate electrode having a first edge in proximity to the field plate, the field plate comprising a second edge facing the first edge, a horizontal distance between the first edge and the second edge is in a range of from about 0.05 to about 0.5 micrometers.

Some embodiments of the present disclosure provide a semiconductor device. The semiconductor device includes a semiconductive substrate. A donor-supply layer is over the semiconductive substrate. The donor-supply layer includes a top surface. A gate structure, a drain, and a source are over the donor-supply layer. A passivation layer covers conformally over the gate structure and the donor-supply layer. A gate electrode is over the gate structure. A field plate is disposed on the passivation layer between the gate electrode and the drain. The field plate includes a bottom edge. The gate electrode having a first edge in proximity to the field plate, the field plate comprising a second edge facing the first edge, a horizontal distance between the first edge and the second edge is in a range of from about 0.05 to about 0.5 micrometers.

Embodiments of the present disclosure disclose a semiconductor device and a manufacturing method thereof. The semiconductor device includes an active region and a passive region surrounding the active region. The semiconductor device further includes a substrate, a multi-layer semiconductor layer located on one side of the substrate, and at least one shielding structure located on one side of the substrate, the shielding structure being electrically connected to a preset potential, for forming an electric field or a zero electric field of the active region pointing toward the passive region.

A semiconductor device includes a first transistor, a first via contact, a second transistor and a second via contact. The first transistor includes a channel and a gate electrode. The first via contact is disposed on the gate electrode of the first transistor, and corresponds in position to the channel of the first transistor. The second transistor includes a channel and a gate electrode. The second via contact is disposed on the gate electrode of the second transistor, and corresponds in position to the channel of the second transistor. A distance between the second via contact and the channel of the second transistor is smaller than a distance between the first via contact and the channel of the first transistor.