A terminal structure of a power device includes a substrate and a plurality of field limiting rings disposed on a first surface of the substrate. The substrate includes a drift layer and a doped layer. The doped layer is formed through diffusion inward from the first surface of the substrate. The doped layer and the drift layer are a first conductivity type, and an impurity concentration of the doped layer is greater than an impurity concentration of the drift layer. The field limiting rings are a second conductivity type. In the terminal structure, lateral diffusion of impurities in the field limiting rings is limited through a design of the doped layer.

A semiconductor device includes a cooling base board and an insulated circuit substrate. On a front surface of an insulated board on the insulated circuit substrate, a high potential circuit pattern on which a semiconductor chip is mounted, an intermediate potential circuit pattern on which a semiconductor chip is mounted, a low potential circuit pattern, and a control circuit pattern are disposed so as to straddle a center line of the cooling base board. The intermediate potential circuit pattern includes a second chip mounting region, an output wiring connection region and an interconnect wiring region that form a U-shaped portion in which the high potential circuit pattern having a semiconductor chip thereon is disposed. The control circuit pattern is disposed so as to straddle the center line and faces the opening of the U-shaped portion.

Semiconductor device including first semiconductor layer of a first conductivity type, second semiconductor layer of a second conductivity type at a surface of the first semiconductor layer, third semiconductor layer of the first conductivity type selectively provided at a surface of the second layer, and gate electrode embedded in a trench via a gate insulating film. The trench penetrates the second and third layers, and reaches the first layer. A thermal oxide film on the third layer has a thickness less than that of the gate insulating film. Also are an interlayer insulating film on the thermal oxide film, barrier metal on an inner surface of a contact hole selectively opened in the thermal oxide film and the interlayer insulating film, metal plug embedded in the contact hole on the barrier metal, and electrode electrically connected to the second and third layers via the barrier metal and the metal plug.

A semiconductor device includes first and second trenches, and a first layer provided therebetween, in a principal surface of a semiconductor substrate, a second layer in contact with and sandwiching the first trench with the first layer, a third layer provided under the second layer and in contact with the second layer and the first trench, a fourth layer provided under and in contact with the third layer but separated from the first trench, and a fifth layer provided in the principal surface and sandwiching the second trench with the first layer. The second and fourth layers are semiconductors of a first conductivity type, and the first, third, and fifth layers are semiconductors of a second conductivity type. A gate trench electrode is provided inside the first trench via the insulating film, and an emitter trench electrode is provided inside the second trench via the insulating film.

A method for producing a silicon carbide component includes forming a silicon carbide layer on an initial wafer, forming a doping region of the silicon carbide component to be produced in the silicon carbide layer, and forming an electrically conductive contact structure of the silicon carbide component to be produced on a surface of the silicon carbide layer. The electrically conductive contact structure electrically contacts the doping region. Furthermore, the method includes splitting the silicon carbide layer or the initial wafer after forming the electrically conductive contact structure, such that a silicon carbide substrate at least of the silicon carbide component to be produced is split off.

A power semiconductor device includes a semiconductor layer, a ladder-shaped trench recessed a specific depth from a surface of the semiconductor layer into the semiconductor layer and including a pair of lines having a first depth and a plurality of connectors connected between the pair of lines and having a second depth shallower than the first depth, a well region defined in the semiconductor layer between the pair of lines and between the plurality of connectors of the trench, a floating region defined in the semiconductor layer outside the pair of lines of the trench, a gate insulating layer disposed on an inner wall of the trench, and a gate electrode layer disposed on the gate insulating layer to fill the trench and including a first portion in which the pair of lines is filled and a second portion in which the plurality of connectors is filled. A depth of the second portion of the gate electrode layer is shallower than a depth of the first portion of the gate electrode layer.

A semiconductor device in which a transistor and a diode are formed on a common semiconductor substrate is provided. The semiconductor substrate includes a transistor region in which a transistor is formed and a diode region in which a diode is formed. At least one first electrode on a second main surface side of the transistor region and at least one second electrode on a second main surface side of the diode region are made of different materials.

A transistor and a diode are formed on a common semiconductor substrate; the semiconductor substrate has a transistor region and an outer peripheral region surrounding it; the transistor region is divided into a plurality of channel regions and a plurality of non-channel regions by a plurality of gate electrodes each having a stripe shape; each of the plurality of non-channel regions has a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, a fifth semiconductor layer, a first electrode, and a second electrode; the third semiconductor layer and the fifth semiconductor layer are electrically connected to the second electrode via a contact hole; and the fifth semiconductor layer is selectively provided not to be in contact with an impurity layer of a first conductivity type that is provided in the outer peripheral region and defines a boundary with a cell region.

All of four of built-in gate resistance trenches function as practical built-in gate resistance trenches. A first end portion of each of four of the built-in gate resistance trenches is electrically connected to a wiring side contact region of a gate wiring via a wiring contact. A second end portion of each of four of the built-in gate resistance trenches is electrically connected to a pad side contact region of a gate pad via a pad contact. In each of four of the built-in gate resistance trenches, a distance between the wiring contact and the pad contact is defined as an inter-contact distance.

A semiconductor device includes a main element and a sense element. Each of the main element and the sense element includes a drift layer, a base layer, an emitter region, a gate insulation film, a gate electrode, and a rear surface layer. The base layer is on the drift layer. The emitter region is at a surface layer portion of the base layer. The gate insulation film is disposed at a surface of the base layer between the emitter region and the drift layer. The gate electrode is on the gate insulation film. The rear surface layer faces the base layer with the drift layer between the rear surface layer and the base layer. The rear surface layer in the main element includes a collector layer. The rear surface layer in the sense element includes a low-impurity layer having smaller amount of impurities than the collector layer.