Presented is a lateral fin static induction transistor including a semi conductive substrate, source and drain regions extending from an optional buffer layer of same or varied thickness supported by the semi conductive substrate, a semi conductive channel electrically coupling the source region to the drain region of the transistor, a portion of the semi conductive channel being a fin and having a face covered by a gated structure, thereby defining a gated channel within the semi conductive channel, the semi conductive channel further including a drift region electrically coupling the gated channel to the drain region of the transistor.

Presented is a lateral fin static induction transistor including a semi conductive substrate, source and drain regions extending from an optional buffer layer of same or varied thickness supported by the semi conductive substrate, a semi conductive channel electrically coupling the source region to the drain region of the transistor, a portion of the semi conductive channel being a fin and having a face covered by a gated structure, thereby defining a gated channel within the semi conductive channel, the semi conductive channel further including a drift region electrically coupling the gated channel to the drain region of the transistor.

Presented is a lateral fin static induction transistor including a semi conductive substrate, source and drain regions extending from an optional buffer layer of same or varied thickness supported by the semi conductive substrate, a semi conductive channel electrically coupling the source region to the drain region of the transistor, a portion of the semi conductive channel being a fin and having a face covered by a gated structure, thereby defining a gated channel within the semi conductive channel, the semi conductive channel further including a drift region electrically coupling the gated channel to the drain region of the transistor.

The field effect transistor (FET) of the present subject matter comprises a bottom gate electrode, a bottom gate dielectric provided on the bottom gate electrode, a channel layer provided on the bottom gate dielectric. A top portion comprising a source electrode, a drain electrode, a top gate electrode provided, and a top dielectric layer is provided on the channel layer. The channel layer forms Schottky barriers at points of contact with the source and the drain electrode. A back-gate voltage varies a height and a top-gate voltage varies a width of the Schottky barrier. The FET can be programmed to work in two operating modes-tunnelling (providing low power consumption) and thermionic mode (providing high performance). The FET can also be programmed to combine the tunnelling and thermionic mode in a single operating cycle, yielding high performance with low power consumption.

A semiconductor device includes a resistive element wherein a diffusion resistance region provided in an upper portion of a semiconductor base and a thin film resistance layer isolated and distanced from the semiconductor base and diffusion resistance region across an insulating film are alternately connected in series and alternately disposed in parallel.

A field-effect transistor and a method for controlling such is provided herein. The field-effect transistor includes a source terminal and a drain terminal arranged on a first side of a semiconductor layer and a single gate arranged on a second side of the semiconductor layer opposite the first side. The gate and the source terminal are arranged to overlap with a first common region of the semiconductor layer and the gate and the drain terminal are arranged to overlap with a second common region of the semiconductor layer.

A silicon carbide (SiC) static induction transistor (SIT) includes a source, a gate disposed over the source and receiving a control signal, a drain disposed over the recessed gate and generating an output signal, an epitaxial pattern disposed between the source and the drain and including a protruding portion, and a gate bus electrically coupled to the gate and including carbon. A method of forming an SiC SIT transistor device includes providing a substrate including a source doped with dopants of a first conductivity type, forming an epitaxial pattern including a protruding portion over the source, forming a recessed gate over the source, forming a gate bus over the recessed gate, forming a drain over the gate bus and the epitaxial pattern, and forming a first heatsink over the drain.

A power conversion apparatus including a transformer, a synchronous rectification (SR) transistor and a SR controller is provided. The SR transistor is coupled between a secondary side of the transformer and an output terminal. The SR controller receives a cross voltage between a drain terminal and a source terminal of the SR transistor as a first detection signal. The SR controller obtains a first time length according to a voltage value of the first detection signal, a voltage value of a first trigger signal and a voltage value of a second trigger signal. The SR controller determines a time point to turn off the SR transistor according to the first time length.