A semiconductor trench capacitor structure is provided. The semiconductor trench capacitor comprises a semiconductor substrate; a trench capacitor overlying the semiconductor substrate, wherein the trench capacitor comprises a plurality of trench electrodes and a plurality of capacitor dielectric layers that are alternatingly stacked over the semiconductor substrate and defines a plurality of trench segments and a plurality of pillar segments, wherein the trench electrodes and the capacitor dielectric layers are recessed into the semiconductor substrate at the trench segments, and wherein the trench segments are separated from each other by the pillar segments; and a protection dielectric layer disposed between the semiconductor substrate and the trench capacitor, wherein the protection dielectric layer has a thickness greater than thicknesses of the trench electrodes.

A semiconductor device includes: a conductive semiconductor substrate in which a trench is formed on the first main surface; a plurality of conductive layers, each of which is either a first conductive layer or a second conductive layer, which are laminated on one another along a surface normal direction of a side surface of the trench; and dielectric layers arranged between a conductive layer closest to the side surface of the trench among the plurality of conductive layers and the side surface of the trench, and between the plurality of corresponding conductive layers. The first conductive layer is electrically insulated from the semiconductor substrate, and the semiconductor substrate that electrically connects to the second conductive layer inside the trench electrically connects to the second electrode.

A multi-voltage domain device includes a semiconductor layer including a first main surface, a second main surface arranged opposite to the first main surface, a first region including first circuity that operates in a first voltage domain, a second region including second circuity that operates in a second voltage domain different than the first voltage domain, and an isolation region that electrically isolates the first region from the second region in a lateral direction that extends parallel to the first and the second main surfaces. The isolation region includes at least one deep trench isolation barrier, each of which extends vertically from the first main surface to the second main surface. The multi-voltage domain device further includes at least one first capacitor configured to generate an electric field laterally across the isolation region between the first region and the second region.

First and second wells are formed in a semiconductor substrate. First and second trenches in the first second wells, respectively, each extend vertically and include a central conductor insulated by a first insulating layer. A second insulating layer is formed on a top surface of the semiconductor substrate. The second insulating layer is selectively thinned over the second trench. A polysilicon layer is deposited on the second insulating layer and then lithographically patterned to form: a first polysilicon portion over the first well that is electrically connected to the central conductor of the first trench to form a first capacitor plate, a second capacitor plate formed by the first well; and a second polysilicon portion over the second well forming a floating gate electrode of a floating gate transistor of a memory cell having an access transistor whose control gate is formed by the central conductor of the second trench.

A semiconductor device has a first trench and a second trench of a trench structure located in a substrate. The second trench is separated from the first trench by a trench space that is less than a first trench width of the first trench and less than a second trench width of the second trench. The trench structure includes a doped sheath having a first conductivity type, contacting and laterally surrounding the first trench and the second trench. The doped sheath extends from the top surface to an isolation layer and from the first trench to the second trench across the trench space. The semiconductor device includes a first region and a second region, both located in the semiconductor layer, having a second, opposite, conductivity type. The first region and the second region are separated by the first trench, the second trench, and the doped sheath.

First and second impurity layers are formed on a first semiconductor layer on a substrate. A third gate insulating layer covers side walls of the impurity layers and the first semiconductor layer. First and second gate conductor layers and a second insulating layer are formed in a groove, and n.sup.+-layers connected to source and bit lines are formed at ends of a second semiconductor layer formed on the second impurity layer and covered with a second gate insulating layer, on which a third gate conductor layer connected to a word line is formed. An operation of maintaining holes generated in a channel region of the second semiconductor layer by impact ionization or a GIDL current near the gate insulating layer and an operation of discharging the holes from the channel region are performed by controlling voltages applied to the source, bit, and word lines and first and second plate lines.

A capacitor structure is provided, which includes a contact layer, an insulating layer, a bottom conductive plate, a dielectric layer and a top conductive plate. The contact layer has first, second, third, fourth and fifth portions arranged from periphery to center. The insulating layer is disposed over the contact layer and has an opening exposing the contact layer. The bottom conductive plate is disposed in the opening and including first, second and third portions extending along a depth direction of the opening and separated from each other and in contact with the first, third and fifth portions of the contact layer, respectively. The dielectric layer is conformally disposed on the bottom conductive plate and in contact with the second and fourth portions of the contact layer. The top conductive plate is disposed on the dielectric layer. A method of manufacturing the capacitor is also provided.

Certain aspects of the present disclosure provide a capacitor assembly, a stacked capacitor assembly, an integrated circuit (IC) assembly comprising such a stacked capacitor assembly, and methods for fabricating the same. One exemplary capacitor assembly generally includes a first array of trench capacitors and a second array of trench capacitors. The second array of trench capacitors may be disposed adjacent to and electrically coupled to the first array of trench capacitors. Additionally, the second array of trench capacitors may be inverted with respect to the first array of trench capacitors.

An electronic component comprising a 3D capacitive structure includes a substrate having a contoured surface comprising a plurality of wells extending from the surface into the substrate body, a dielectric formed over, and conforming to the shape of, the contoured surface, and a first electrode formed over the dielectric and conforming to the contoured surface shape. The substrate constitutes a second electrode and the dielectric is interposed between it and the first electrode. Portions of the dielectric are exposed through openings at the base of the contoured surface and contact an insulating layer formed under the substrate, reducing the electrostatic field arising in the contacted portions of the dielectric when a potential difference is applied between the first and second electrodes. The openings at the bottom of the wells are obturated by the dielectric, defining blind holes within the wells, and the first electrode is in the blind holes.

A semiconductor region includes an isolating region which delimits a working area of the semiconductor region. A trench is located in the working area and further extends into the isolating region. The trench is filled by an electrically conductive central portion that is insulated from the working area by an isolating enclosure. A cover region is positioned to cover at least a first part of the filled trench, wherein the first part is located in the working area. A dielectric layer is in contact with the filled trench. A metal silicide layer is located at least on the electrically conductive central portion of a second part of the filled trench, wherein the second part is not covered by the cover region.