A capacitance structure includes a first input terminal configured to input a first input signal, a first output terminal configured to output the first output signal, a second input terminal configured to input a second input signal, a second output terminal configured to output a second output signal, and a plurality of trench cells. Each of the plurality of trench cells includes a first electrode and a second electrode. The first electrodes of the plurality of trenches are interconnected to form a first electrode of the capacitor structure, the second electrodes of the plurality of trench cells are interconnected to form a second electrode of the capacitor structure, the first electrode of the capacitor structure is connected to the first input signal, and the second electrode of the capacitor structure is connected to the input second signal.

An electrode is included in a base substrate. A trench is produced in the base substrate. The trench is filled with an annealed amorphous material to form the electrode. The electrode is made of a crystallized material which includes particles that are implanted into a portion of the electrode that is located adjacent the front-face side of the base substrate.

A semiconductor device and methods of formation are provided herein. A semiconductor device includes a conductor concentrically surrounding an insulator, and the insulator concentrically surrounding a column. The conductor, the insulator and the conductor are alternately configured to be a transistor, a resistor, or a capacitor. The column also functions as a via to send signals from a first layer to a second layer of the semiconductor device. The combination of via and at least one of a transistor, a capacitor, or a resistor in a semiconductor device decreases an area penalty as compared to a semiconductor device that has vias formed separately from at least one of a transistor, a capacitor, or resistor.

The present disclosure, in some embodiments, relates to a method of forming a capacitor structure. The method includes forming a capacitor dielectric layer over a lower electrode layer, and forming an upper electrode layer over the capacitor dielectric layer. The upper electrode layer is etched to define an upper electrode and to expose a part of the capacitor dielectric layer. A spacer structure is formed over horizontally extending surfaces of the upper electrode layer and the capacitor dielectric layer and also along sidewalls of the upper electrode. The spacer structure is etched to remove the spacer structure from over the horizontally extending surfaces of the upper electrode layer and the capacitor dielectric layer and to define a spacer. The capacitor dielectric layer and the lower electrode layer are etched according to the spacer to define a capacitor dielectric and a lower electrode.

Provided are a semiconductor structure and a method for manufacturing the semiconductor structure. The semiconductor structure includes a substrate in which a capacitor structure is formed, and the capacitor structure includes a lower electrode plate, a dielectric layer, an upper electrode plate and a protective layer. The lower electrode plate is located on the substrate. The dielectric layer covers a surface of the lower electrode plate. The upper electrode plate covers the dielectric layer. The protective layer is formed on a surface of the upper electrode plate parallel to the substrate.

In a general aspect, a semiconductor device can include a semiconductor region, an active region disposed in the semiconductor region, and a termination region disposed on the semiconductor region and adjacent to the active region. The termination region can include a trench having a conductive material disposed therein. The termination region can further include a first cavity separating the trench from the semiconductor region. A portion of the first cavity can be disposed between a bottom of the trench and the semiconductor region. The termination region can also include a second cavity separating the trench from the semiconductor region.

The invention concerns an implementable semiconductor device that includes an electrode configured to be in contact with biological tissue and at least one capacitor, and wherein the capacitor includes a capacitor electrode having a first surface facing and in contact with the electrode configured to be in contact with biological tissue.

A semiconductor device and methods for making the same are disclosed. The device may include: a first transistor structure; a second transistor structure; a capacitor structure comprising a trench in the substrate between the first and second transistor structures, the capacitor structure further comprising a doped layer over the substrate, a dielectric layer over the doped layer, and a conductive fill material over the dielectric layer; a first conductive contact from the first transistor structure to a first bit line; a second conductive contact from the second transistor to a non-volatile memory element; and a third conductive contact from the non-volatile memory element to a second bit line.

An embodiment a structure including a first semiconductor device bonded to a first side of a first redistribution structure by first conductive connectors, the first semiconductor device comprising a first plurality of passive elements formed on a first substrate, the first redistribution structure comprising a plurality of dielectric layers with metallization patterns therein, the metallization patterns of the first redistribution structure being electrically coupled to the first plurality of passive elements, a second semiconductor device bonded to a second side of the first redistribution structure by second conductive connectors, the second side of the first redistribution structure being opposite the first side of the first redistribution structure, the second semiconductor device comprising a second plurality of passive elements formed on a second substrate, the metallization patterns of the first redistribution structure being electrically coupled to the second plurality of passive elements.

A semiconductor device and a method of forming the same are provided. The semiconductor device includes a substrate, a deep trench capacitor (DTC) within the substrate, and an interconnect structure over the DTC and the substrate. The interconnect structure includes a seal ring structure in electrical contact with the substrate, a first conductive via in electrical contact with the DTC, and a first conductive line electrically coupling the seal ring structure to the first conductive via.