A peeling method at low cost with high mass productivity is provided. An oxide layer is formed over a formation substrate, a first layer is formed over the oxide layer using a photosensitive material, an opening is formed in a portion of the first layer that overlaps with the oxide layer by a photolithography method and the first layer is heated to form a resin layer having an opening, a transistor including an oxide semiconductor in a channel formation region is formed over the resin layer, a conductive layer is formed to overlap with the opening of the resin layer and the oxide layer, the oxide layer is irradiated with light using a laser, and the transistor and the formation substrate are separated from each other.

A method for dividing a wafer including: attaching a protective tape to a functional layer of the wafer with the adhesive layer of the tape in contact with the functional layer; and a wafer dividing step. The dividing step includes a cut groove forming step and a laser processing step. The cut groove forming step uses a blade to form a cut groove with a depth that does not reach the functional layer, resulting in part of the substrate being left along each division line. The laser processing step includes applying a laser beam to the part of the substrate left after the cut groove forming step and the functional layer of the wafer to form a laser processed groove having a depth reaching the tape. The tape is closely attached to the functional layer during the tape attaching step to prevent the adhesion of debris to the devices.

In a wafer processing method, the back side of a wafer is attached to an adhesive tape supported at its peripheral portion by an annular frame having an inside opening. The wafer is set in the inside opening, thereby supporting the wafer through the adhesive tape to the annular frame. The wafer is held on a chuck table with the front side of the wafer facing the upper surface of the chuck table. A laser beam is applied through the adhesive tape and the back side of the wafer in an area corresponding to each division line, thereby forming a plurality of shield tunnels arranged along each division line. Each shield tunnel extends from the front side of the wafer to the back side thereof, each shield tunnel being composed of a fine hole and an amorphous region formed around the fine hole for shielding the fine hole.

A semiconductor device and a method of manufacturing a semiconductor device. For example, various aspects of this disclosure provide a semiconductor device having an ultra-thin substrate, and a method of manufacturing a semiconductor device having an ultra-thin substrate. As a non-limiting example, a substrate structure comprising a carrier, an adhesive layer formed on the carrier, and an ultra-thin substrate formed on the adhesive layer may be received and/or formed, components may then be mounted to the ultra-thin substrate and encapsulated, and the carrier and adhesive layer may then be removed.

A support substrate, a method of manufacturing a semiconductor package, and a semiconductor package, the support substrate including a first plate; a second plate on the first plate; and an adhesive layer between the first plate and the second plate, wherein a coefficient of thermal expansion (CTE) of the adhesive layer is higher than a CTE of the first plate and higher than a CTE of the second plate.

A semiconductor device has a first semiconductor die stacked over a second semiconductor die which is mounted to a temporary carrier. A plurality of bumps is formed over an active surface of the first semiconductor die around a perimeter of the second semiconductor die. An encapsulant is deposited over the first and second semiconductor die and carrier. A plurality of conductive vias is formed through the encapsulant around the first and second semiconductor die. A portion of the encapsulant and a portion of a back surface of the first and second semiconductor die is removed. An interconnect structure is formed over the encapsulant and the back surface of the first or second semiconductor die. The interconnect structure is electrically connected to the conductive vias. The carrier is removed. A heat sink or shielding layer can be formed over the encapsulant and first semiconductor die.

A method of dividing a single-crystal substrate along a plurality of preset division lines, includes a shield tunnel forming step of applying a pulsed laser beam having such a wavelength that permeates through the substrate along the division lines to form shield tunnels, each including a fine hole and an amorphous region shielding the fine hole, a protective member adhering step of adhering a protective member to the substrate before or after the shield tunnel forming step, and a grinding step of holding the protective member on the substrate, to which the shield tunnel forming step and the protective member adhering step are performed, on a chuck table of a grinding apparatus, grinding a reverse surface of the substrate to bring the substrate to a predetermined thickness, and dividing the substrate along the division lines along which the shield tunnels have been formed.

Embodiments of the present disclosure relate to a method for manufacturing a display panel. The method includes providing a hardness-variable material layer and a flexible layer on the hardness-variable material layer, and bonding a chip to the flexible layer. The hardness-variable material layer is set to be in a hard state before bonding the chip to the flexible layer. After bonding the chip to the flexible layer, the hardness-variable material layer is peeled off. The hardness-variable material layer is set to be in a flexible state before peeling off the hardness-variable material layer.

A production method for a semiconductor element (10) includes: a semiconductor element forming step of forming the semiconductor element (10) including a dielectric film (3); a dicing region forming step of forming dicing regions (11) by removing the dielectric film (3) in partition regions that partition the semiconductor element (10); and a dicing step of dicing the dicing regions (11).

The invention provides an electronic device package and fabrication method thereof. The electronic device package includes a sensor chip. An upper surface of the sensor chip comprises a sensing film. A covering plate having an opening structure covers the upper surface of the sensor chip. A cavity is between the covering plate and the sensor chip, corresponding to a position of the sensing film, where the cavity communicates with the opening structure. A spacer is between the covering plate and the sensor chip, surrounding the cavity. A pressure releasing region is between the spacer and the sensing film.