A wafer-level chip-size package includes a semiconductor structure. A bonding pad is formed over the semiconductor structure, including a plurality of conductive segments. A conductive component is formed over the semiconductor structure, being adjacent to the bonding pad. A passivation layer is formed, exposing a portions of the conductive segments of the first bonding pad. A conductive redistribution layer is formed over the portions of the conductive segments of the first bonding pad exposed by the passivation layer. A planarization layer is formed over the passivation layer and the conductive redistribution layer, exposing a portion of the conductive redistribution layer. A UBM layer is formed over the planarization layer and the portion of the conductive redistribution layer exposed by the planarization layer. A conductive bump is formed over the UBM layer.

A semiconductor device includes a semiconductor layer that has a main surface, an electrode pad that is formed on the main surface, a rewiring that has a first wiring surface connected to the electrode pad and a second wiring surface positioned on a side opposite to the first wiring surface and being roughened, the rewiring being formed on the main surface such as to be drawn out to a region outside the electrode pad, and a resin that covers the second wiring surface on the main surface and that seals the rewiring.

A semiconductor device includes an insulation layer, wires, a semiconductor element, and an encapsulation resin. The insulation layer includes a main surface and a back surface facing opposite in a thickness-wise direction and a side surface formed between the main surface and the back surface in the thickness-wise direction. The wires include an embedded portion embedded in the insulation layer and a redistribution portion formed of a metal film joined to the embedded portion and formed from the back surface to the side surface. The semiconductor element is mounted on the main surface and includes electrodes joined to at least part of the embedded portion of the wires. The encapsulation resin contacts the main surface and covers the semiconductor element.

An integrated circuit (IC) device includes a redistribution line over a substrate, wherein an entire sidewall of the redistribution line is curved. The IC device further includes a passivation layer over the redistribution line, wherein a distance from a bottommost surface of the passivation layer to the substrate is less than a distance from a bottommost surface of the redistribution line to the substrate. The IC device further includes a polymer layer over the passivation layer.

An electrical component including a substrate, a first dielectric layer on the substrate, a redistribution layer pad on the first dielectric layer, and a component interconnection element on the redistribution layer pad so that the component interconnection element fills an opening in the second dielectric layer. The opening includes at least one protrusion between the component interconnection element solder ball metallization and the redistribution layer pad.

A structure includes first and second substrates, first and second stress buffer layers, and a post-passivation interconnect (PPI) structure. The first and second substrates include first and second semiconductor substrates and first and second interconnect structures on the first and second semiconductor substrates, respectively. The second interconnect structure is on a first side of the second semiconductor substrate. The first substrate is bonded to the second substrate at a bonding interface. A via extends at least through the second semiconductor substrate into the second interconnect structure. The first stress buffer layer is on a second side of the second semiconductor substrate opposite from the first side of the second semiconductor substrate. The PPI structure is on the first stress buffer layer and is electrically coupled to the via. The second stress buffer layer is on the PPI structure and the first stress buffer layer.

Provided is a semiconductor memory device and a method of manufacturing the semiconductor memory device. The semiconductor memory device includes a first circuit structure, a first conductive line connected to the first circuit structure, a second conductive line facing the first conductive line, and a second circuit structure overlapping with the first circuit structure with the first and second conductive lines interposed therebetween, the second circuit structure being connected to the second conductive line. One of the first conductive line and the second conductive line has a region protruding toward the other of the first conductive line and the second conductive line.

A semiconductor device includes a semiconductor layer that has a main surface, a trench gate structure that includes a trench formed in the main surface and having a first sidewall at one side, a second sidewall at the other side and a bottom wall in a cross-sectional view, an insulation layer formed on an inner wall of the trench, and a gate electrode embedded in the trench with the insulation layer between the trench and the gate electrode and having an upper end portion positioned at a bottom-wall side with respect to the main surface, a plurality of first-conductivity-type drift regions that are respectively formed in a region at the first sidewall side of the trench and in a region at the second sidewall side of the trench such as to face each other with the trench interposed therebetween in a surface layer portion of the main surface and that are positioned in a region at the main surface side with respect to the bottom wall, and a plurality of first-conductivity-type source/drain regions that are formed in surface layer portions of the plurality of drift regions, respectively.

A method of manufacturing a semiconductor device is provided. The method includes depositing a non-conductive layer over a semiconductor die. An opening is formed in the non-conductive layer exposing a portion of a bond pad of the semiconductor die. A cavity is in the non-conductive layer with a portion of the non-conductive layer remaining between a bottom surface of the cavity and a bottom surface of the non-conductive layer. A conductive layer is formed over the non-conductive layer and the portion of the bond pad. The conductive layer is configured to interconnect the bond pad with a conductive layer portion over the cavity.

Disclosed is a semiconductor package comprising a semiconductor chip, an external connection member on the semiconductor chip, and a dielectric film between the semiconductor chip and the external connection member. The semiconductor chip includes a substrate, a front-end-of-line structure on the substrate, and a back-end-of-line structure on the front-end-of-line structure. The back-end-of-line structure includes metal layers stacked on the front-end-of-line structure, a first dielectric layer on the uppermost metal layer and including a contact hole that vertically overlaps a pad of an uppermost metal layer, a redistribution line on the first dielectric layer and including a contact part in the contact hole and electrically connected to the pad, a pad part, and a line part that electrically connects the contact part to the pad part, and an upper dielectric layer on the redistribution line.