A sintering powder comprising copper particles, wherein: the particles are at least partially coated with a capping agent, and the particles exhibit a D10 of greater than or equal to 100 nm and a D90 of less than or equal to 2000 nm.

The power semiconductor apparatus includes: a semiconductor device 401; a bonding layer on chip 416 disposed on an upper surface of the semiconductor device; and a metal lead 419 disposed on the upper surface of the semiconductor device and bonded to the bonding layer on chip, wherein the metal lead 420 has a three-laminated structure including: a second metal layer 420b having a CTE equal to or less than 510.sup.6/ C., for example; and a first metal layer 420a and a third metal layer 420c sandwiching the second metal layer and having a CTE equal to or greater than the CTE of the second metal layer. Provided is a power semiconductor apparatus capable of improving reliability thereof by reducing a thermal stress to a bonding layer between a semiconductor power device and a metal lead positioned on an upper surface thereof, and reducing a resistance of the metal lead.

A semiconductor device of the present invention includes a circuit layer formed of a conductive material, a semiconductor element mounted on a first surface of the circuit layer, and a ceramic substrate disposed on a second surface of the circuit layer, in which a Ag underlayer having a glass layer and a Ag layer laminated on the glass layer is formed on the first surface of the circuit layer, and the Ag layer of the Ag underlayer and the semiconductor element are directly joined together.

The present invention discloses a power semiconductor module, comprising: a substrate; a semiconductor provided on a top side of the substrate; and a package formed on the semiconductor and the substrate, wherein the package has openings at a top side thereof, through which terminal contacts of the semiconductor and the substrate are exposed outside and accessible from outside.

According to various embodiments, a method for processing a substrate may include: processing a plurality of device regions in a substrate separated from each other by dicing regions, each device region including at least one electronic component; wherein processing each device region of the plurality of device regions includes: forming a recess into the substrate in the device region, wherein the recess is defined by recess sidewalls of the substrate, wherein the recess sidewalls are arranged in the device region; forming a contact pad in the recess to electrically connect the at least one electronic component, wherein the contact pad has a greater porosity than the recess sidewalls; and singulating the plurality of device regions from each other by dicing the substrate in the dicing region.

A method includes placing an electronic device on a pliable mating surface on a major surface of a mold such that at least one contact pad on the electronic device presses against the pliable mating surface. The pliable mating surface is on a microstructure in an arrangement of microstructures on the major surface of the mold. A liquid encapsulant material is applied over the electronic device and the major surface of the mold, and then hardened to form a carrier for the electronic device. The mold and the carrier are separated such that the microstructures on the mold form a corresponding arrangement of microchannels in the carrier, and at least one contact pad on the electronic device is exposed in a microchannel in the arrangement of microchannels. A conductive particle-containing liquid is deposited in the microchannel, which directly contacts the contact pad exposed in the microchannel.

A chip comprising a non-conductive substrate layer and at least one conductor path disposed on the substrate layer, the solder contact surface being at least partially formed on the conductor path, and a method for producing the solder contact surface on the chip including the steps of: applying a sinter paste to a contact location at least partially located on the conductor path, the sinter paste comprising particles of at least one soft-solderable and conductive material and at least one solvent; and evaporating the solvent.

An Ag underlayer-attached metallic member includes a metallic member joined with a body to be joined and an Ag underlayer formed on a joining surface of the metallic member with the body to be joined, the Ag underlayer includes a glass layer formed on a metallic member side and an Ag layer laminated on the glass layer, and an area proportion of voids in an Ag layer surface of the Ag underlayer is 25% or less.

An Ag underlayer-attached metallic member includes a metallic member joined with a body to be joined and an Ag underlayer formed on a joining surface of the metallic member with the body to be joined, the Ag underlayer includes a glass layer formed on a metallic member side and an Ag layer laminated on the glass layer, and an area proportion of voids in an Ag layer surface of the Ag underlayer is 25% or less.

A semiconductor device of the present invention includes a circuit layer formed of a conductive material, a semiconductor element mounted on a first surface of the circuit layer, and a ceramic substrate disposed on a second surface of the circuit layer, in which a Ag underlayer having a glass layer and a Ag layer laminated on the glass layer is formed on the first surface of the circuit layer, and the Ag layer of the Ag underlayer and the semiconductor element are directly joined together.