A groove is formed between an inner peripheral edge of an opening of a pad electrode and an outer peripheral edge of a bonding region located inside the pad electrode in plan view.

A method of manufacturing a wafer assembly includes forming an array of planar wafer level metal posts extending from a surface of a substrate of a first wafer. After forming the array of posts, an oxide layer is applied over the surface of the first wafer and around the array of posts, the oxide layer being applied at a temperature of below 150 degrees Celsius.

An integrated circuit chip includes an SOI substrate having a structure in which a bulk substrate, a buried insulating film, and a semiconductor body layer are sequentially stacked, a conductive ion implantation region formed at a position adjacent to the buried insulating film in the bulk substrate, an integrated circuit portion formed on an active surface of the semiconductor body layer, and a penetrating electrode portion arranged at a position spaced apart from the integrated circuit portion in a horizontal direction, the penetrating electrode portion penetrating the semiconductor body layer and the buried insulating layer in a vertical direction, and the penetrating electrode portion connected to the conductive ion implantation region. An integrated circuit package and a display device include the integrated circuit chip.

An integrated circuit chip includes an SOI substrate having a structure in which a bulk substrate, a buried insulating film, and a semiconductor body layer are sequentially stacked, a conductive ion implantation region formed at a position adjacent to the buried insulating film in the bulk substrate, an integrated circuit portion formed on an active surface of the semiconductor body layer, and a penetrating electrode portion arranged at a position spaced apart from the integrated circuit portion in a horizontal direction, the penetrating electrode portion penetrating the semiconductor body layer and the buried insulating layer in a vertical direction, and the penetrating electrode portion connected to the conductive ion implantation region. An integrated circuit package and a display device include the integrated circuit chip.

Various embodiments of the present disclosure are directed towards an integrated circuit (IC) chip comprising a semiconductor device that is inverted and that overlies a dielectric region inset into a top of a semiconductor substrate. An interconnect structure overlies the semiconductor substrate and the dielectric region and further comprises an intermetal dielectric (IMD) layer. The IMD layer is bonded to the top of the semiconductor substrate and accommodates a pad. A semiconductor layer overlies the interconnect structure, and the semiconductor device is in the semiconductor layer, between the semiconductor layer and the interconnect structure. The semiconductor device comprises a first source/drain electrode overlying the dielectric region and further overlying and electrically coupled to the pad. The dielectric region reduces substrate capacitance to decrease substrate power loss and may, for example, be a cavity or a dielectric layer. A contact extends through the semiconductor layer to the pad.

A semiconductor device includes a first plurality of dies encapsulated by an encapsulant, an interposer over the first plurality of dies, an interconnect structure over and electrically connected to the interposer, and a plurality of conductive pads on a surface of the interconnect structure opposite the interposer. The interposer includes a plurality of embedded passive components. Each die of the first plurality of dies is electrically connected to the interposer. The interconnect structure includes a solenoid inductor in a metallization layer of the interconnect structure.

A semiconductor device and method is disclosed. The semiconductor device may include a semiconductor substrate including an active area, a metal layer structure over the active area, wherein the metal layer structure is configured to form an electrical contact, the metal layer structure including a solder area, a buffer area, and a barrier area between the solder area and the buffer area, wherein, in the barrier area, the metal layer structure is further away from the active area than in the solder area and in the buffer area, and wherein each of the solder area and the buffer area is in direct contact with the active area or with a wiring layer structure arranged between the active area and the metal layer structure.

A semiconductor device and method is disclosed. The semiconductor device may include a semiconductor substrate including an active area, a metal layer structure over the active area, wherein the metal layer structure is configured to form an electrical contact, the metal layer structure including a solder area, a buffer area, and a barrier area between the solder area and the buffer area, wherein, in the barrier area, the metal layer structure is further away from the active area than in the solder area and in the buffer area, and wherein each of the solder area and the buffer area is in direct contact with the active area or with a wiring layer structure arranged between the active area and the metal layer structure.

The present disclosure provides a die assembly. The die assembly includes a first die, a second die and a third die stacked together. The first die includes a plurality of first metal lines facing a plurality of second metal lines of the second die, and a second substrate beneath the second metal lines faces a plurality of third metal lines of the third die. The die assembly further includes at least one first plug, a first redistribution layer and a second redistribution layer. The first plug penetrates through the second substrate to connect to at least one of the second metal lines. A first redistribution layer physically connects at least one of the first metal lines to at least one of the second metal lines, and a second redistribution layer physically connects at least one of the third metal lines to the first plug.

The present application provides a semiconductor package with air gaps for reducing capacitive coupling between conductive features and a method for manufacturing the semiconductor package. The semiconductor package includes a first semiconductor structure and a second semiconductor structure bonded with the first semiconductor structure. The first semiconductor structure has a first bonding surface. The second semiconductor structure has a second bonding surface partially in contact with the first bonding surface. A portion of the first bonding surface is separated from a portion of the second bonding surface, a space between the portions of the first and second bonding surfaces is sealed and forms an air gap in the semiconductor package.