A semiconductor device includes a first plurality of dies encapsulated by an encapsulant, an interposer over the first plurality of dies, an interconnect structure over and electrically connected to the interposer, and a plurality of conductive pads on a surface of the interconnect structure opposite the interposer. The interposer includes a plurality of embedded passive components. Each die of the first plurality of dies is electrically connected to the interposer. The interconnect structure includes a solenoid inductor in a metallization layer of the interconnect structure.

A semiconductor die (“die”) employing repurposed seed layer for forming additional signal paths to a back end-of-line (BEOL) structure of the die, and related integrated circuit (IC) packages and fabrication methods. A seed layer is repurposed that was disposed adjacent the BEOL interconnect structure to couple an under bump metallization (UBM) interconnect without a coupled interconnect bump thus forming an unraised interconnect bump, to a UBM interconnect that has a raised interconnect bump. To couple the unraised interconnect bump to the raised interconnect bump, the seed layer is selectively removed during fabrication to leave a portion of the seed layer repurposed that couples the UBM interconnect that does not have an interconnect bump to the UBM interconnect that has a raised interconnect bump. Additional routing paths can be provided between raised interconnect bumps to the BEOL interconnect structure through coupling of UBM interconnects to an unraised interconnect bump.

The present application provides a semiconductor structure having a porous structure between a conductive pad and a metal layer. The semiconductor structure includes: a substrate including an interconnection structure; a dielectric layer disposed over the substrate; a conductive pad disposed over the dielectric layer; a passivation layer, disposed over the dielectric layer and partially exposing the conductive pad; and a porous layer, surrounded by the dielectric layer and extending between the substrate and the conductive pad.

A method for forming a semiconductor structure is provided. The method includes forming a contact feature over an insulating layer, forming a first passivation layer over the contact feature, and etching the first passivation layer to form a trench exposing the contact feature. The method also includes forming an oxide layer over the contact feature and the first passivation layer and in the trench, forming a first non-conductive structure over the oxide layer, and patterning the first non-conductive structure to form a gap. The method further includes filling a conductive material in the gap to form a first conductive feature. The first non-conductive structure and the first conductive feature form a first bonding structure. The method further includes attaching a carrier substrate to the first bonding structure via a second bonding structure over the carrier substrate.

A semiconductor device includes a device layer, a first passivation layer, an aluminum pad, a second passivation layer, an under-ball metallurgy (UBM) pad and a connector. The device layer is disposed over a substrate, wherein the device layer includes a top metal feature. The first passivation layer is disposed over the device layer. The aluminum pad penetrates through the first passivation layer and is electrically connected to the top metal feature. The second passivation layer is disposed over the aluminum pad. The UBM pad penetrates through the second passivation layer and is electrically connected to the aluminum pad. The connector is disposed over the UBM pad. In some embodiments, a first included angle between a sidewall and a bottom of the aluminum pad is greater than a second included angle between a sidewall and a bottom of the UBM pad.

Various embodiments of the present application are directed towards a pad with high strength and bondability. In some embodiments, an integrated chip comprises a substrate, an interconnect structure, a pad, and a conductive structure. The interconnect structure adjoins the substrate and comprises wires and vias. The wires and the vias are stacked between the pad and the substrate. The conductive structure (e.g., a wire bond) extends through the substrate to the pad. By arranging the wires and the vias between the pad and the substrate, the pad may be inset into a passivation layer of the interconnect structure and the passivation layer may absorb stress on the pad. Further, the pad may contact the wires and the vias at a top wire level. A thickness of the top wire level may exceed a thickness of other wire levels, whereby the top wire level may be more tolerant to stress.

An electronic device substrate with a substantially planar surface formed from an electrically non-conductive material is provided with one or more metalized pads on the substantially planner surface. Each of the one or more metalized pads is surrounded by and coplanar with the first electrically nonconductive material along an outer boundary of the metalized pad. The metalized pad is patterned such that portions of the metalized pad form metalized fingers that extend radially from the outer boundary of the metalized pad in an interdigitated arrangement with the first electrically nonconductive material. The metalized pad has a solderable surface.

A display backboard and a manufacturing method thereof, and a display device are provided. The display backboard includes: a driving substrate; a plurality of driving electrodes on the driving substrate; and a plurality of connection structures respectively on the plurality of driving electrodes. The connection structure includes: at least one conductive component on the driving electrode; and a restriction component on a side of the driving electrodes provided with the at least one conductive component and in at least a part of a peripheral region of the at least one conductive component. The restriction component protrudes from the driving electrode and has a first height in a direction perpendicular to the driving substrate.

The present application provides a semiconductor package with air gaps for reducing capacitive coupling between conductive features and a method for manufacturing the semiconductor package. The semiconductor package includes a first semiconductor structure and a second semiconductor structure bonded with the first semiconductor structure. The first semiconductor structure has a first bonding surface. The second semiconductor structure has a second bonding surface partially in contact with the first bonding surface. A portion of the first bonding surface is separated from a portion of the second bonding surface, a space between the portions of the first and second bonding surfaces is sealed and forms an air gap in the semiconductor package.

A method includes forming a conductive pad over an interconnect structure of a wafer, forming a capping layer over the conductive pad, forming a dielectric layer covering the capping layer, and etching the dielectric layer to form an opening in the dielectric layer. The capping layer is exposed to the opening. A wet-cleaning process is then performed on the wafer. During the wet-cleaning process, a top surface of the capping layer is exposed to a chemical solution used for performing the wet-cleaning process. The method further includes depositing a conductive diffusion barrier extending into the opening, and depositing a conductive material over the conductive diffusion barrier.