A semiconductor die (“die”) employing repurposed seed layer for forming additional signal paths to a back end-of-line (BEOL) structure of the die, and related integrated circuit (IC) packages and fabrication methods. A seed layer is repurposed that was disposed adjacent the BEOL interconnect structure to couple an under bump metallization (UBM) interconnect without a coupled interconnect bump thus forming an unraised interconnect bump, to a UBM interconnect that has a raised interconnect bump. To couple the unraised interconnect bump to the raised interconnect bump, the seed layer is selectively removed during fabrication to leave a portion of the seed layer repurposed that couples the UBM interconnect that does not have an interconnect bump to the UBM interconnect that has a raised interconnect bump. Additional routing paths can be provided between raised interconnect bumps to the BEOL interconnect structure through coupling of UBM interconnects to an unraised interconnect bump.

Provided is a circuit structure including a substrate, a pad, a dielectric layer, a conductive layer, an adhesion layer, and a conductive bump. The pad is disposed on the substrate. The dielectric layer is disposed on the substrate and exposes a portion of the pad. The conductive layer contacts the pad and extends from the pad to cover a top surface of the dielectric layer. The adhesion layer is disposed between the dielectric layer and the conductive layer. The conductive bump extends in an upward manner from a top surface of the conductive layer. The conductive bump and the conductive layer are integrally formed. A method of manufacturing the circuit structure is also provided.

A semiconductor structure includes a first semiconductor package, a second semiconductor package, a heat spreader and an underfill layer. The first semiconductor package includes a plurality of lower semiconductor chips and a first dielectric encapsulation layer disposed around the plurality of the lower semiconductor chips. The second semiconductor package is disposed over and corresponds to one of the plurality of lower semiconductor chips, wherein the second semiconductor package includes a plurality of upper semiconductor chips and a second dielectric encapsulation layer disposed around the plurality of upper semiconductor chips. The heat spreader is disposed over and corresponds to another of the plurality of lower semiconductor chips. The underfill layer is disposed over the first semiconductor package and around the second semiconductor package and the heat spreader.

Provided are a solid-state image-capturing device, a semiconductor apparatus, an electronic apparatus, and a manufacturing method that enable improvement in reliability of through electrodes and increase in density of through electrodes. A common opening portion is formed including a through electrode formation region that is a region in which the plurality of through electrodes electrically connected respectively to a plurality of electrode pads provided on a joint surface side from a device formation surface of a semiconductor substrate is formed. A plurality of through portions is formed so as to penetrate to the plurality of respective electrode pads in the common opening portion, and wiring is formed along the common opening portion and the through portions from the electrode pads to the device formation surface corresponding to the respective through electrodes. The present technology can be applied to a layer-type solid-state image-capturing device, for example.

The present disclosure provides a redistribution layer (RDL) structure, a semiconductor device and manufacturing method thereof. The semiconductor device comprising an RDL structure that may include a substrate, a first conductive layer, a reinforcement layer and, and a second conductive layer. The first conductive layer may be formed on the substrate and has a first bond pad area. The reinforcement layer may be formed on a surface of the first conductive layer facing away from the substrate and located in the first bond pad area. The second conductive layer may be formed on the reinforcement layer and an area of the first conductive layer not covered by the reinforcement layer. The reinforcement layer has a material strength greater than those of the first conductive layer and the second conductive layer.

There is provided semiconductor devices and methods of forming the same, the semiconductor devices including: a first semiconductor element having a first electrode; a second semiconductor element having a second electrode; a Sn-based micro-solder bump formed on the second electrode; and a concave bump pad including the first electrode opposite to the micro-solder bump, where the first electrode is connected to the second electrode via the micro-solder bump and the concave bump pad.

A semiconductor package includes a first semiconductor chip having a first substrate, a first insulating layer on the first substrate, and a plurality of first bonding pads on the first insulating layer, and having a flat upper surface by an upper surface of the first insulating layer and upper surfaces of the plurality of first bonding pads; and a second semiconductor chip on the upper surface of the first semiconductor chip and having a second substrate, a second insulating layer below the second substrate and in contact with the first insulating layer, and a plurality of second bonding pads on the second insulating layer and in contact with the first bonding pads, respectively, wherein the first insulating layer includes an insulating interfacial layer in contact with the second insulating layer, embedded in the first insulating layer, and spaced apart from the plurality of first bonding pads.

The present description relates to a method of manufacturing an electronic circuit (30) comprising: a support (32), an assembly site (31) having a first surface protruding from said support intended to be assembled to an assembly site of another electronic circuit by a self-assembly method; and a peripheral area (39) around said assembly site, the assembly site (31) comprising at least one level, each level comprising conductive pads (34) and insulating posts (380) between the conductive pads, said manufacturing method comprising the forming of said at least one level of the assembly site, such that the edges, in at least one direction (X) of the main plane (XY), of each level of the assembly site and the locations, in the at least one direction (X), of the conductive pads and of the insulating posts of the same level are defined in a same photolithography step of said method.

A semiconductor package includes a substrate, a first insulation layer, a conductive via and a conductive trace. The substrate includes a conductive component. The first insulation layer is formed on the substrate and having a first through hole exposing the conductive component. The conductive via is formed within the first through hole. The conductive trace is directly connected to the conductive via which is located directly above the first through hole.

A device structure, along with methods of forming such, are described. The device structure includes a structure, a first passivation layer disposed on the structure, a buffer layer disposed on the first passivation layer, a barrier layer disposed on a first portion of the buffer layer, a redistribution layer disposed over the barrier layer, an adhesion layer disposed on the barrier layer and on side surfaces of the redistribution layer, and a second passivation layer disposed on a second portion of the buffer layer. The second passivation layer is in contact with the barrier layer, the adhesion layer, and the redistribution layer.